#define CTRL_OFFSET 0x2c
#define CTRL_INTER_CLKEN 0x1
-#define CTRL_INTER_CLKRDY 0x1
-#define CTRL_INTER_CLKOUT 0x1
+#define CTRL_INTER_CLKRDY 0x2
+#define CTRL_INTER_CLKOUT 0x4
#define PHYCTRL_PDB_MASK 0x1
#define PHYCTRL_PDB_SHIFT 0x0
#define PHYCTRL_PDB_PWR_ON 0x1
#define PHYCTRL_OTAPDLYENA_SHIFT 11
#define PHYCTRL_OTAPDLYSEL_MASK 0xf
#define PHYCTRL_OTAPDLYSEL_SHIFT 7
+#define PHYCTRL_REN_STRB_ENABLE 0x1
+#define PHYCTRL_REN_STRB_MASK 0x1
+#define PHYCTRL_REN_STRB_SHIFT 9
struct rockchip_emmc_phy {
unsigned int reg_offset;
PHYCTRL_OTAPDLYENA_MASK,
PHYCTRL_OTAPDLYENA_SHIFT));
+ regmap_write(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_CON2,
+ HIWORD_UPDATE(PHYCTRL_REN_STRB_ENABLE,
+ PHYCTRL_REN_STRB_MASK,
+ PHYCTRL_REN_STRB_SHIFT));
+
regmap_write(rk_phy->reg_base,
rk_phy->reg_offset + GRF_EMMCPHY_CON0,
HIWORD_UPDATE(rk_phy->opdelay,