[dfsan] Introduce an optimization to reduce the number of union queries.

[oota-llvm.git] / docs / index.rst

diff --git a/docs/index.rst b/docs/index.rst
index aec897b9ea9f3be258d226bd64945d607e088839..1d4fbd9d34d0c03799bc09ae49dc57d1fc762f5e 100644 (file)
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -215,6 +215,7 @@ For API clients and LLVM developers.
 
    AliasAnalysis
    BitCodeFormat
+   BlockFrequencyTerminology
    BranchWeightMetadata
    Bugpoint
    CodeGenerator
@@ -236,6 +237,7 @@ For API clients and LLVM developers.
    NVPTXUsage
    StackMaps
    InAlloca
+   BigEndianNEON
 
 :doc:`WritingAnLLVMPass`
    Information on how to write LLVM transformations and analyses.
@@ -248,7 +250,7 @@ For API clients and LLVM developers.
    working on retargetting LLVM to a new architecture, designing a new codegen
    pass, or enhancing existing components.
 
-:doc:`TableGenFundamentals`
+:doc:`TableGen <TableGen/index>`
    Describes the TableGen tool, which is used heavily by the LLVM code
    generator.
 
@@ -298,6 +300,10 @@ For API clients and LLVM developers.
 :doc:`BranchWeightMetadata`
    Provides information about Branch Prediction Information.
 
+:doc:`BlockFrequencyTerminology`
+   Provides information about terminology used in the ``BlockFrequencyInfo``
+   analysis pass.
+
 :doc:`SegmentedStacks`
    This document describes segmented stacks and how they are used in LLVM.
 
@@ -314,6 +320,11 @@ For API clients and LLVM developers.
   LLVM support for mapping instruction addresses to the location of
   values and allowing code to be patched.
 
+:doc:`BigEndianNEON`
+  LLVM's support for generating NEON instructions on big endian ARM targets is
+  somewhat nonintuitive. This document explains the implementation and rationale.
+
+
 Development Process Documentation
 =================================