as "Instruction".</p>
<p><b>TableGen multiclasses</b> are groups of abstract records that are
-instantiated all at once. Each instantiation can result in multiple TableGen
-definitions.</p>
+instantiated all at once. Each instantiation can result in multiple
+TableGen definitions. If a multiclass inherits from another multiclass,
+the definitions in the sub-multiclass become part of the current
+multiclass, as if they were declared in the current multiclass.</p>
</div>
<b>bit</b> isIndirectBranch = 0;
<b>bit</b> isBarrier = 0;
<b>bit</b> isCall = 0;
- <b>bit</b> isSimpleLoad = 0;
+ <b>bit</b> canFoldAsLoad = 0;
<b>bit</b> mayLoad = 0;
<b>bit</b> mayStore = 0;
<b>bit</b> isImplicitDef = 0;
<dd>string value</dd>
<dt><tt>[{ ... }]</tt></dt>
<dd>code fragment</dd>
-<dt><tt>[ X, Y, Z ]</tt></dt>
- <dd>list value.</dd>
+<dt><tt>[ X, Y, Z ]<type></tt></dt>
+ <dd>list value. <type> is the type of the list
+element and is usually optional. In rare cases,
+TableGen is unable to deduce the element type in
+which case the user must specify it explicitly.</dd>
<dt><tt>{ a, b, c }</tt></dt>
<dd>initializer for a "bits<3>" value</dd>
<dt><tt>value</tt></dt>
<dd>a dag value. The first element is required to be a record definition, the
remaining elements in the list may be arbitrary other values, including nested
`<tt>dag</tt>' values.</dd>
+<dt><tt>(implicit a)</tt></dt>
+ <dd>an implicitly defined physical register. This tells the dag instruction
+ selection emitter the input pattern's extra definitions matches implicit
+ physical register definitions.</dd>
+<dt><tt>(parallel (a), (b))</tt></dt>
+ <dd>a list of dags specifying parallel operations which map to the same
+ instruction.</dd>
<dt><tt>!strconcat(a, b)</tt></dt>
<dd>A string value that is the result of concatenating the 'a' and 'b'
strings.</dd>
+<dt><tt>!cast<type>(a)</tt></dt>
+ <dd>A symbol of type <em>type</em> obtained by looking up the string 'a' in
+the symbol table. If the type of 'a' does not match <em>type</em>, TableGen
+aborts with an error. !cast<string> is a special case in that the argument must
+be an object defined by a 'def' construct.</dd>
+<dt><tt>!nameconcat<type>(a, b)</tt></dt>
+ <dd>Shorthand for !cast<type>(!strconcat(a, b))</dd>
+<dt><tt>!subst(a, b, c)</tt></dt>
+ <dd>If 'a' and 'b' are of string type or are symbol references, substitute
+'b' for 'a' in 'c.' This operation is analogous to $(subst) in GNU make.</dd>
+<dt><tt>!foreach(a, b, c)</tt></dt>
+ <dd>For each member 'b' of dag or list 'a' apply operator 'c.' 'b' is a
+dummy variable that should be declared as a member variable of an instantiated
+class. This operation is analogous to $(foreach) in GNU make.</dd>
+<dt><tt>!car(a)</tt></dt>
+ <dd>The first element of list 'a.'</dd>
+<dt><tt>!cdr(a)</tt></dt>
+ <dd>The 2nd-N elements of list 'a.'</dd>
+<dt><tt>!null(a)</tt></dt>
+ <dd>An integer {0,1} indicating whether list 'a' is empty.</dd>
+<dt><tt>!if(a,b,c)</tt></dt>
+ <dd>'b' if the result of integer operator 'a' is nonzero, 'c' otherwise.</dd>
</dl>
<p>Note that all of the values have rules specifying how they convert to values
<p>The name of the resultant definitions has the multidef fragment names
appended to them, so this defines <tt>ADD_rr</tt>, <tt>ADD_ri</tt>,
- <tt>SUB_rr</tt>, etc. Using a multiclass this way is exactly equivalent to
- instantiating the classes multiple times yourself, e.g. by writing:</p>
+ <tt>SUB_rr</tt>, etc. A defm may inherit from multiple multiclasses,
+ instantiating definitions from each multiclass. Using a multiclass
+ this way is exactly equivalent to instantiating the classes multiple
+ times yourself, e.g. by writing:</p>
<div class="doc_code">
<pre>
end-user to factor out commonality from the records.</p>
<p>File-scope "let" expressions take a comma-separated list of bindings to
-apply, and one of more records to bind the values in. Here are some
+apply, and one or more records to bind the values in. Here are some
examples:</p>
<div class="doc_code">
<b>let</b> Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] <b>in</b> {
- <b>def</b> CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
- "call\t${dst:call}", []>;
- <b>def</b> CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
- "call\t{*}$dst", [(X86call GR32:$dst)]>;
- <b>def</b> CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
- "call\t{*}$dst", []>;
+ <b>def</b> CALLpcrel32 : Ii32<0xE8, RawFrm, (outs), (ins i32imm:$dst,variable_ops),
+ "call\t${dst:call}", []>;
+ <b>def</b> CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
+ "call\t{*}$dst", [(X86call GR32:$dst)]>;
+ <b>def</b> CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
+ "call\t{*}$dst", []>;
}
</pre>
</div>
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<a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
<a href="http://llvm.org">LLVM Compiler Infrastructure</a><br>