======================
-LLVM 3.3 Release Notes
+LLVM 3.5 Release Notes
======================
.. contents::
:local:
.. warning::
- These are in-progress notes for the upcoming LLVM 3.3 release. You may
- prefer the `LLVM 3.2 Release Notes <http://llvm.org/releases/3.2/docs
+ These are in-progress notes for the upcoming LLVM 3.5 release. You may
+ prefer the `LLVM 3.4 Release Notes <http://llvm.org/releases/3.4/docs
/ReleaseNotes.html>`_.
============
This document contains the release notes for the LLVM Compiler Infrastructure,
-release 3.3. Here we describe the status of LLVM, including major improvements
+release 3.5. Here we describe the status of LLVM, including major improvements
from the previous release, improvements in various subprojects of LLVM, and
some of the current users of the code. All LLVM releases may be downloaded
from the `LLVM releases web site <http://llvm.org/releases/>`_.
Non-comprehensive list of changes in this release
=================================================
-.. NOTE
- For small 1-3 sentence descriptions, just add an entry at the end of
- this list. If your description won't fit comfortably in one bullet
- point (e.g. maybe you would like to give an example of the
- functionality, or simply have a lot to talk about), see the `NOTE` below
- for adding a new subsection.
-
-* The CellSPU port has been removed. It can still be found in older versions.
-
-* The IR-level extended linker APIs (for example, to link bitcode files out of
- archives) have been removed. Any existing clients of these features should
- move to using a linker with integrated LTO support.
+* All backends have been changed to use the MC asm printer and support for the
+ non MC one has been removed.
-* LLVM and Clang's documentation has been migrated to the `Sphinx
- <http://sphinx-doc.org/>`_ documentation generation system which uses
- easy-to-write reStructuredText. See `llvm/docs/README.txt` for more
- information.
+* Clang can now successfully self-host itself on Linux/Sparc64 and on
+ FreeBSD/Sparc64.
-* TargetTransformInfo (TTI) is a new interface that can be used by IR-level
- passes to obtain target-specific information, such as the costs of
- instructions. Only "Lowering" passes such as LSR and the vectorizer are
- allowed to use the TTI infrastructure.
+* LLVM now assumes the assembler supports ``.loc`` for generating debug line
+ numbers. The old support for printing the debug line info directly was only
+ used by ``llc`` and has been removed.
-* We've improved the X86 and ARM cost model.
+* All inline assembly is parsed by the integrated assembler when it is enabled.
+ Previously this was only the case for object-file output. It is now the case
+ for assembly output as well. The integrated assembler can be disabled with
+ the ``-no-integrated-as`` option.
-* The Attributes classes have been completely rewritten and expanded. They now
- support not only enumerated attributes and alignments, but "string"
- attributes, which are useful for passing information to code generation. See
- :doc:`HowToUseAttributes` for more details.
+* llvm-ar now handles IR files like regular object files. In particular, a
+ regular symbol table is created for symbols defined in IR files, including
+ those in file scope inline assembly.
-* TableGen's syntax for instruction selection patterns has been simplified.
- Instead of specifying types indirectly with register classes, you should now
- specify types directly in the input patterns. See ``SparcInstrInfo.td`` for
- examples of the new syntax. The old syntax using register classes still
- works, but it will be removed in a future LLVM release.
+* LLVM now always uses cfi directives for producing most stack
+ unwinding information.
-* MCJIT now supports exception handling. Support for it in the old jit will be
- removed in the 3.4 release.
+* The prefix for loop vectorizer hint metadata has been changed from
+ ``llvm.vectorizer`` to ``llvm.loop.vectorize``. In addition,
+ ``llvm.vectorizer.unroll`` metadata has been renamed
+ ``llvm.loop.interleave.count``.
-* Command line options can now be grouped into categories which are shown in
- the output of ``-help``. See :ref:`grouping options into categories`.
+* Some backends previously implemented Atomic NAND(x,y) as ``x & ~y``. Now
+ all backends implement it as ``~(x & y)``, matching the semantics of GCC 4.4
+ and later.
-* The appearance of command line options in ``-help`` that are inherited by
- linking with libraries that use the LLVM Command line support library can now
- be modified at runtime. See :ref:`cl::getRegisteredOptions`.
+.. NOTE
+ For small 1-3 sentence descriptions, just add an entry at the end of
+ this list. If your description won't fit comfortably in one bullet
+ point (e.g. maybe you would like to give an example of the
+ functionality, or simply have a lot to talk about), see the `NOTE` below
+ for adding a new subsection.
* ... next change ...
Makes programs 10x faster by doing Special New Thing.
-AArch64 target
---------------
-
-We've added support for AArch64, ARM's 64-bit architecture. Development is still
-in fairly early stages, but we expect successful compilation when:
+Changes to the ARM Backend
+--------------------------
+
+Since release 3.3, a lot of new features have been included in the ARM
+back-end but weren't production ready (ie. well tested) on release 3.4.
+Just after the 3.4 release, we started heavily testing two major parts
+of the back-end: the integrated assembler (IAS) and the ARM exception
+handling (EHABI), and now they are enabled by default on LLVM/Clang.
+
+The IAS received a lot of GNU extensions and directives, as well as some
+specific pre-UAL instructions. Not all remaining directives will be
+implemented, as we made judgement calls on the need versus the complexity,
+and have chosen simplicity and future compatibility where hard decisions
+had to be made. The major difference is, as stated above, the IAS validates
+all inline ASM, not just for object emission, and that cause trouble with
+some uses of inline ASM as pre-processor magic.
+
+So, while the IAS is good enough to compile large projects (including most
+of the Linux kernel), there are a few things that we can't (and probably
+won't) do. For those cases, please use ``-fno-integrated-as`` in Clang.
+
+Exception handling is another big change. After extensive testing and
+changes to cooperate with Dwarf unwinding, EHABI is enabled by default.
+The options ``-arm-enable-ehabi`` and ``-arm-enable-ehabi-descriptors``,
+which were used to enable EHABI in the previous releases, are removed now.
-- compiling standard compliant C99 and C++03 with Clang;
-- using Linux as a target platform;
-- where code + static data doesn't exceed 4GB in size (heap allocated data has
- no limitation).
+This means all ARM code will emit EH unwind tables, or CFI unwinding (for
+debug/profiling), or both. To avoid run-time inconsistencies, C code will
+also emit EH tables (in case they interoperate with C++ code), as is the
+case for other architectures (ex. x86_64).
-Some additional functionality is also implemented, notably DWARF debugging,
-GNU-style thread local storage and inline assembly.
+Changes to the MIPS Target
+--------------------------
-Hexagon Target
---------------
+There has been a large amount of improvements to the MIPS target which can be
+broken down into subtarget, ABI, and Integrated Assembler changes.
-- Removed support for legacy hexagonv2 and hexagonv3 processor
- architectures which are no longer in use. Currently supported
- architectures are hexagonv4 and hexagonv5.
+Subtargets
+^^^^^^^^^^
-Loop Vectorizer
----------------
+Added support for Release 6 of the MIPS32 and MIPS64 architecture (MIPS32r6
+and MIPS64r6). Release 6 makes a number of significant changes to the MIPS32
+and MIPS64 architectures. For example, FPU registers are always 64-bits wide,
+FPU NaN values conform to IEEE 754 (2008), and the unaligned memory instructions
+(such as lwl and lwr) have been replaced with a requirement for ordinary memory
+operations to support unaligned operations. Full details of MIPS32 and MIPS64
+Release 6 can be found on the `MIPS64 Architecture page at Imagination
+Technologies <http://www.imgtec.com/mips/architectures/mips64.asp>`_.
-We've continued the work on the loop vectorizer. The loop vectorizer now
-has the following features:
+This release also adds experimental support for MIPS-IV, cnMIPS, and Cavium
+Octeon CPU's.
-- Loops with unknown trip counts.
-- Runtime checks of pointers.
-- Reductions, Inductions.
-- Min/Max reductions of integers.
-- If Conversion.
-- Pointer induction variables.
-- Reverse iterators.
-- Vectorization of mixed types.
-- Vectorization of function calls.
-- Partial unrolling during vectorization.
+Support for the MIPS SIMD Architecture (MSA) has been improved to support MSA
+on MIPS64.
-The loop vectorizer is now enabled by default for -O3.
+Support for IEEE 754 (2008) NaN values has been added.
-SLP Vectorizer
---------------
+ABI and ABI extensions
+^^^^^^^^^^^^^^^^^^^^^^
-LLVM now has a new SLP vectorizer. The new SLP vectorizer is not enabled by
-default but can be enabled using the clang flag -fslp-vectorize. The BB-vectorizer
-can also be enabled using the command line flag -fslp-vectorize-aggressive.
+There has also been considerable ABI work since the 3.4 release. This release
+adds support for the N32 ABI, the O32-FPXX ABI Extension, the O32-FP64 ABI
+Extension, and the O32-FP64A ABI Extension.
-R600 Backend
-------------
+The N32 ABI is an existing ABI that has now been implemented in LLVM. It is a
+64-bit ABI that is similar to N64 but retains 32-bit pointers. N64 remains the
+default 64-bit ABI in LLVM. This differs from GCC where N32 is the default
+64-bit ABI.
-The R600 backend was added in this release, it supports AMD GPUs
-(HD2XXX - HD7XXX). This backend is used in AMD's Open Source
-graphics / compute drivers which are developed as part of the `Mesa3D
-<http://www.mesa3d.org>`_ project.
-
-SystemZ/s390x Backend
----------------------
-
-LLVM and clang now support IBM's z/Architecture. At present this support
-is restricted to GNU/Linux (GNU triplet s390x-linux-gnu) and requires
-z10 or greater.
-
-
-Sub-project Status Update
-============================================
+The O32-FPXX ABI Extension is 100% compatible with the O32-ABI and the O32-FP64
+ABI Extension and may be linked with either but may not be linked with both of
+these simultaneously. It extends the O32 ABI to allow the same code to execute
+without modification on processors with 32-bit FPU registers as well as 64-bit
+FPU registers. The O32-FPXX ABI Extension is enabled by default for the O32 ABI
+on mips*-img-linux-gnu and mips*-mti-linux-gnu triples and is selected with
+-mfpxx. It is expected that future releases of LLVM will enable the FPXX
+Extension for O32 on all triples.
-In addition to the core LLVM 3.3 distribution of production-quality compiler
-infrastructure, the LLVM project includes sub-projects that use the LLVM core
-and share the same distribution license. This section provides updates on
-these sub-projects.
+The O32-FP64 ABI Extension is an extension to the O32 ABI to fully exploit FPU's
+with 64-bit registers and is enabled with -mfp64. This replaces an undocumented
+and unsupported O32 extension which was previously enabled with -mfp64. It is
+100% compatible with the O32-FPXX ABI Extension.
+The O32-FP64A ABI Extension is a restricted form of the O32-FP64 ABI Extension
+which allows interlinking with unmodified binaries that use the base O32 ABI.
-LLDB: Low Level Debugger
-------------------------
+Integrated Assembler
+^^^^^^^^^^^^^^^^^^^^
-`LLDB <http://lldb.llvm.org/>`_ is a ground-up implementation of a command-line
-debugger, as well as a debugger API that can be used from scripts and other
-applications. LLDB uses the following components of the LLVM core distribution
-to support the latest language features and target support:
+The MIPS Integrated Assembler has undergone a substantial overhaul including a
+rewrite of the assembly parser. It's not ready for general use in this release
+but adventurous users may wish to enable it using ``-fintegrated-as``.
-- the Clang parser for high-quality parsing of C, C++ and Objective C
-- the LLVM disassembler
-- the LLVM JIT compiler (MCJIT) for expression evaluation
+In this release, the integrated assembler supports the majority of MIPS-I,
+MIPS-II, MIPS-III, MIPS-IV, MIPS-V, MIPS32, MIPS32r2, MIPS32r6, MIPS64,
+MIPS64r2, and MIPS64r6 as well as some of the Application Specific Extensions
+such as MSA. It also supports several of the MIPS specific assembler directives
+such as ``.set``, ``.module``, ``.cpload``, etc.
-The `3.3 release <http://llvm.org/apt/>`_ has the following notable changes.
+Changes to the PowerPC Target
+-----------------------------
+
+The PowerPC 64-bit Little Endian subtarget (powerpc64le-unknown-linux-gnu) is
+now fully supported. This includes support for the Altivec instruction set.
+
+The Power Architecture 64-Bit ELFv2 ABI Specification is now supported, and
+is the default ABI for Little Endian. The ELFv1 ABI remains the default ABI
+for Big Endian. Currently, it is not possible to override these defaults.
+That capability will be available (albeit not recommended) in a future release.
+
+Links to the ELFv2 ABI specification and to the Power ISA Version 2.07
+specification may be found `here <https://www-03.ibm.com/technologyconnect/tgcm/TGCMServlet.wss?alias=OpenPOWER&linkid=1n0000>`_ (free registration required).
+Efforts are underway to move this to a location that doesn't require
+registration, but the planned site isn't ready yet.
-Linux Features:
+Experimental support for the VSX instruction set introduced with ISA 2.06
+is now available using the ``-mvsx`` switch. Work remains on this, so it
+is not recommended for production use. VSX is disabled for Little Endian
+regardless of this switch setting.
-- Support for watchpoints
-- vim integration for lldb commands and program status using a `vim plug-in <http://llvm.org/svn/llvm-project/lldb/trunk/utils/vim-lldb/README>`_
-- Improved register support including vector registers
-- Builds with cmake/ninja/auto-tools/clang 3.3/gcc 4.6
+Load/store cost estimates have been improved.
-Linux Improvements:
+Constant hoisting has been enabled.
-- Debugging multi-threaded programs
-- Debugging i386 programs
-- Process list, attach and fork
-- Expression evaluation
+Global named register support has been enabled.
+Initial support for PIC code has been added for the 32-bit ELF subtarget.
+Further support will be available in a future release.
-External Open Source Projects Using LLVM 3.3
+External Open Source Projects Using LLVM 3.5
============================================
An exciting aspect of LLVM is that it is used as an enabling technology for
a lot of other language and tools projects. This section lists some of the
-projects that have already been updated to work with LLVM 3.3.
-
-
-Portable Computing Language (pocl)
-----------------------------------
-
-In addition to producing an easily portable open source OpenCL
-implementation, another major goal of `pocl <http://pocl.sourceforge.net/>`_
-is improving performance portability of OpenCL programs with
-compiler optimizations, reducing the need for target-dependent manual
-optimizations. An important part of pocl is a set of LLVM passes used to
-statically parallelize multiple work-items with the kernel compiler, even in
-the presence of work-group barriers. This enables static parallelization of
-the fine-grained static concurrency in the work groups in multiple ways.
-
-TTA-based Co-design Environment (TCE)
--------------------------------------
-
-`TCE <http://tce.cs.tut.fi/>`_ is a toolset for designing new
-processors based on the Transport triggered architecture (TTA).
-The toolset provides a complete co-design flow from C/C++
-programs down to synthesizable VHDL/Verilog and parallel program binaries.
-Processor customization points include the register files, function units,
-supported operations, and the interconnection network.
-
-TCE uses Clang and LLVM for C/C++/OpenCL C language support, target independent
-optimizations and also for parts of code generation. It generates new
-LLVM-based code generators "on the fly" for the designed TTA processors and
-loads them in to the compiler backend as runtime libraries to avoid
-per-target recompilation of larger parts of the compiler chain.
-
-Just-in-time Adaptive Decoder Engine (Jade)
--------------------------------------------
-
-`Jade <https://github.com/orcc/jade>`_ (Just-in-time Adaptive Decoder Engine)
-is a generic video decoder engine using LLVM for just-in-time compilation of
-video decoder configurations. Those configurations are designed by MPEG
-Reconfigurable Video Coding (RVC) committee. MPEG RVC standard is built on a
-stream-based dataflow representation of decoders. It is composed of a standard
-library of coding tools written in RVC-CAL language and a dataflow
-configuration --- block diagram --- of a decoder.
-
-Jade project is hosted as part of the Open RVC-CAL Compiler
-(`Orcc <http://orcc.sf.net>`_) and requires it to translate the RVC-CAL standard
-library of video coding tools into an LLVM assembly code.
-
-LDC - the LLVM-based D compiler
--------------------------------
-
-`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It
-pragmatically combines efficiency, control, and modeling power, with safety and
-programmer productivity. D supports powerful concepts like Compile-Time Function
-Execution (CTFE) and Template Meta-Programming, provides an innovative approach
-to concurrency and offers many classical paradigms.
-
-`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler
-combined with LLVM as backend to produce efficient native code. LDC targets
-x86/x86_64 systems like Linux, OS X and Windows and also Linux/PPC64. Ports to
-other architectures like ARM are underway.
+projects that have already been updated to work with LLVM 3.5.
Additional Information
projects / oota-llvm.git / blobdiff