[docs] Fix some Sphinx warnings that have crept in.

[oota-llvm.git] / docs / LangRef.rst

diff --git a/docs/LangRef.rst b/docs/LangRef.rst
index d18d4ebac9089936335c384fa9ce1b185bbb4952..0654ca62e3dbc3f4290b3869217e56f501b9d985 100644 (file)
--- a/docs/LangRef.rst
+++ b/docs/LangRef.rst
@@ -681,6 +681,10 @@ the aliasee.
 
 The aliasee must be a definition.
 
+Aliases are not allowed to point to aliases with linkages that can be
+overridden. Since they are only a second name, the possibility of the
+intermediate alias being overridden cannot be represented in an object file.
+
 .. _namedmetadatastructure:
 
 Named Metadata
@@ -765,8 +769,6 @@ Currently, only the following parameter attributes are defined:
 
 ``inalloca``
 
-.. Warning:: This feature is unstable and not fully implemented.
-
     The ``inalloca`` argument attribute allows the caller to take the
     address of outgoing stack arguments.  An ``inalloca`` argument must
     be a pointer to stack memory produced by an ``alloca`` instruction.
@@ -6116,7 +6118,7 @@ Overview:
 """""""""
 
 The '``select``' instruction is used to choose one value based on a
-condition, without branching.
+condition, without IR-level branching.
 
 Arguments:
 """"""""""
@@ -6952,22 +6954,25 @@ Syntax:
 Overview:
 """""""""
 
-The '``llvm.clear_cache``' intrinsic provides access to the systemcall
-that flushes the cache at the range specified. Some targets need this
-to specifically flush the instruction cache when executable data changes
-in memory (self-modifying code). Other targets have unified intruction
-and data cache, so they don't need any calls.
+The '``llvm.clear_cache``' intrinsic ensures visibility of modifications
+in the specified range to the execution unit of the processor. On
+targets with non-unified instruction and data cache, the implementation
+flushes the instruction cache.
 
 Semantics:
 """"""""""
 
-When directly supported, this intrinsic will either return a call to
-the appropriate cache clearing system call (usually ``__clear_cache``)
-when the caches are not unified (ARM, Mips) or just remove the call
-altogether when they are (ex. x86_64).
+On platforms with coherent instruction and data caches (e.g. x86), this
+intrinsic is a nop. On platforms with non-coherent instruction and data
+cache (e.g. ARM, MIPS), the intrinsic is lowered either to appropiate
+instructions or a system call, if cache flushing requires special
+privileges.
+
+The default behavior is to emit a call to ``__clear_cache`` from the run
+time library.
 
-Targets must implement it directly to have either behaviour, as the
-default is to bail with "Not Implemented" message.
+This instrinsic does *not* empty the instruction pipeline. Modifications
+of the current function are outside the scope of the intrinsic.
 
 Standard C Library Intrinsics
 -----------------------------