<li><a href="#codegendesc">Machine code description classes</a>
<ul>
<li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
+ <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
+ class</a></li>
+ <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
</ul>
</li>
<li><a href="#codegenalgs">Target-independent code generation algorithms</a>
<li><a href="#selectiondag_optimize">SelectionDAG Optimization
Phase: the DAG Combiner</a></li>
<li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
- <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Emission
+ <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Phase</a></li>
<li><a href="#selectiondag_future">Future directions for the
SelectionDAG</a></li>
</ul></li>
+ <li><a href="#codeemit">Code Emission</a>
+ <ul>
+ <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
+ <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
+ </ul></li>
</ul>
</li>
- <li><a href="#targetimpls">Target description implementations</a>
+ <li><a href="#targetimpls">Target-specific Implementation Notes</a>
<ul>
<li><a href="#x86">The X86 backend</a></li>
</ul>
but could be required for radically different targets that do not fit into the
LLVM machine description model: programmable FPGAs for example.</p>
-<p><b>Important Note:</b> For historical reasons, the LLVM SparcV9 code
-generator uses almost entirely different code paths than described in this
-document. For this reason, there are some deprecated interfaces (such as
-<tt>TargetRegInfo</tt> and <tt>TargetSchedInfo</tt>), which are only used by the
-V9 backend and should not be used by any other targets. Also, all code in the
-<tt>lib/Target/SparcV9</tt> directory and subdirectories should be considered
-deprecated, and should not be used as the basis for future code generator work.
-The SparcV9 backend is slowly being merged into the rest of the
-target-independent code generators, but this is a low-priority process with no
-predictable completion date.</p>
-
</div>
<!-- ======================================================================= -->
generation in this model is divided into the following stages:</p>
<ol>
-<li><b><a href="#instselect">Instruction Selection</a></b> - Determining an
-efficient implementation of the input LLVM code in the target instruction set.
+<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
+determines an efficient way to express the input LLVM code in the target
+instruction set.
This stage produces the initial code for the program in the target instruction
set, then makes use of virtual registers in SSA form and physical registers that
represent any required register assignments due to target constraints or calling
-conventions.</li>
+conventions. This step turns the LLVM code into a DAG of target
+instructions.</li>
+
+<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
+phase takes the DAG of target instructions produced by the instruction selection
+phase, determines an ordering of the instructions, then emits the instructions
+as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
+that we describe this in the <a href="#instselect">instruction selection
+section</a> because it operates on a <a
+href="#selectiondag_intro">SelectionDAG</a>.
+</li>
<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
optional stage consists of a series of machine-code optimizations that
operate on the SSA-form produced by the instruction selector. Optimizations
-like modulo-scheduling, normal scheduling, or peephole optimization work here.
+like modulo-scheduling or peephole optimization work here.
</li>
-<li><b><a name="#regalloc">Register Allocation</a></b> - The
+<li><b><a href="#regalloc">Register Allocation</a></b> - The
target code is transformed from an infinite virtual register file in SSA form
to the concrete register file used by the target. This phase introduces spill
code and eliminates all virtual register references from the program.</li>
-<li><b><a name="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
+<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
machine code has been generated for the function and the amount of stack space
required is known (used for LLVM alloca's and spill slots), the prolog and
epilog code for the function can be inserted and "abstract stack location
references" can be eliminated. This stage is responsible for implementing
optimizations like frame-pointer elimination and stack packing.</li>
-<li><b><a name="latemco">Late Machine Code Optimizations</a></b> - Optimizations
+<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
that operate on "final" machine code can go here, such as spill code scheduling
and peephole optimizations.</li>
-<li><b><a name="codemission">Code Emission</a></b> - The final stage actually
+<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
puts out the code for the current function, either in the target assembler
format or in machine code.</li>
repetition.
</p>
+<p>As LLVM continues to be developed and refined, we plan to move more and more
+of the target description to be in <tt>.td</tt> form. Doing so gives us a
+number of advantages. The most important is that it makes it easier to port
+LLVM, because it reduces the amount of C++ code that has to be written and the
+surface area of the code generator that needs to be understood before someone
+can get in an get something working. Second, it is also important to us because
+it makes it easier to change things: in particular, if tables and other things
+are all emitted by tblgen, we only need to change one place (tblgen) to update
+all of the targets to a new interface.</p>
+
</div>
<!-- *********************************************************************** -->
target machine; independent of any particular client. These classes are
designed to capture the <i>abstract</i> properties of the target (such as the
instructions and registers it has), and do not incorporate any particular pieces
-of code generation algorithms. These interfaces do not take interference graphs
-as inputs or other algorithm-specific data structures.</p>
+of code generation algorithms.</p>
<p>All of the target description classes (except the <tt><a
href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
<div class="doc_text">
<p>The <tt>TargetData</tt> class is the only required target description class,
-and it is the only class that is not extensible. You cannot derived a new
-class from it. <tt>TargetData</tt> specifies information about how the target
+and it is the only class that is not extensible (you cannot derived a new
+class from it). <tt>TargetData</tt> specifies information about how the target
lays out memory for structures, the alignment requirements for various data
types, the size of pointers in the target, and whether the target is
little-endian or big-endian.</p>
<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
selectors primarily to describe how LLVM code should be lowered to SelectionDAG
operations. Among other things, this class indicates:
-<ul><li>an initial register class to use for various ValueTypes,</li>
- <li>which operations are natively supported by the target machine,</li>
- <li>the return type of setcc operations, and</li>
- <li>the type to use for shift amounts, etc</li>.
+<ul><li>an initial register class to use for various ValueTypes</li>
+ <li>which operations are natively supported by the target machine</li>
+ <li>the return type of setcc operations</li>
+ <li>the type to use for shift amounts</li>
+ <li>various high-level characteristics, like whether it is profitable to turn
+ division by a constant into a multiplication sequence</li>
</ol></p>
</div>
-
-
-
-
<!-- ======================================================================= -->
<div class="doc_subsection">
<a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
<p>Registers in the code generator are represented in the code generator by
unsigned numbers. Physical registers (those that actually exist in the target
description) are unique small numbers, and virtual registers are generally
-large.</p>
+large. Note that register #0 is reserved as a flag value.</p>
<p>Each register in the processor description has an associated
<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the register
<div class="doc_text">
<p>
- TODO
+ <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
+ specific chip set being targeted. A sub-target informs code generation of
+ which instructions are supported, instruction latencies and instruction
+ execution itinerary; i.e., which processing units are used, in what order, and
+ for how long.
</p>
</div>
<p>
At the high-level, LLVM code is translated to a machine specific representation
-formed out of MachineFunction, MachineBasicBlock, and <a
+formed out of <a href="#machinefunction">MachineFunction</a>,
+<a href="#machinebasicblock">MachineBasicBlock</a>, and <a
href="#machineinstr"><tt>MachineInstr</tt></a> instances
(defined in include/llvm/CodeGen). This representation is completely target
agnostic, representing instructions in their most abstract form: an opcode and a
</div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
+</div>
+
+<div class="doc_text">
+
+<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
+(<a href="#machineinstr">MachineInstr</a> instances). It roughly corresponds to
+the LLVM code input to the instruction selector, but there can be a one-to-many
+mapping (i.e. one LLVM basic block can map to multiple machine basic blocks).
+The MachineBasicBlock class has a "<tt>getBasicBlock</tt>" method, which returns
+the LLVM basic block that it comes from.
+</p>
+
+</div>
+
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
+</div>
+
+<div class="doc_text">
+
+<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
+(<a href="#machinebasicblock">MachineBasicBlock</a> instances). It corresponds
+one-to-one with the LLVM function input to the instruction selector. In
+addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
+the MachineConstantPool, MachineFrameInfo, MachineFunctionInfo,
+SSARegMap, and a set of live in and live out registers for the function. See
+<tt>MachineFunction.h</tt> for more information.
+</p>
+
+</div>
+
+
+
<!-- *********************************************************************** -->
<div class="doc_section">
<a name="codegenalgs">Target-independent code generation algorithms</a>
<div class="doc_text">
<p>This section documents the phases described in the <a
-href="high-level-design">high-level design of the code generator</a>. It
+href="#high-level-design">high-level design of the code generator</a>. It
explains how they work and some of the rationale behind their design.</p>
</div>
The SelectionDAG provides an abstraction for code representation in a way that
is amenable to instruction selection using automatic techniques
(e.g. dynamic-programming based optimal pattern matching selectors), It is also
-well suited to other phases of code generation; in particular, instruction scheduling. Additionally, the SelectionDAG provides a host representation where a
-large variety of very-low-level (but target-independent)
+well suited to other phases of code generation; in particular,
+instruction scheduling (SelectionDAG's are very close to scheduling DAGs
+post-selection). Additionally, the SelectionDAG provides a host representation
+where a large variety of very-low-level (but target-independent)
<a href="#selectiondag_optimize">optimizations</a> may be
performed: ones which require extensive information about the instructions
efficiently supported by the target.
<p>
The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
-operation code (Opcode) that indicates what operation the node performs.
+operation code (Opcode) that indicates what operation the node performs and
+the operands to the operation.
The various operation node types are described at the top of the
-<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file. Depending on the
-operation, nodes may contain additional information (e.g. the condition code
-for a SETCC node) contained in a derived class.</p>
+<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
<p>Although most operations define a single value, each node in the graph may
define multiple values. For example, a combined div/rem operation will define
<p>
One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal"
DAG. A legal DAG for a target is one that only uses supported operations and
-supported types. On PowerPC, for example, a DAG with any values of i1, i8, i16,
-or i64 type would be illegal. The <a href="#selectiondag_legalize">legalize</a>
+supported types. On a 32-bit PowerPC, for example, a DAG with any values of i1,
+i8, i16,
+or i64 type would be illegal, as would a DAG that uses a SREM or UREM operation.
+The <a href="#selectiondag_legalize">legalize</a>
phase is responsible for turning an illegal DAG into a legal DAG.
</p>
</div>
the target instruction selector matches the DAG operations to target
instructions. This process translates the target-independent input DAG into
another DAG of target instructions.</li>
-<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Emission</a>
+<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
- The last phase assigns a linear order to the instructions in the
target-instruction DAG and emits them into the MachineFunction being
compiled. This step uses traditional prepass scheduling techniques.</li>
<p>After all of these steps are complete, the SelectionDAG is destroyed and the
rest of the code generation passes are run.</p>
+<p>One great way to visualize what is going on here is to take advantage of a
+few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
+option pops up a window with the SelectionDAG input to the Select phase for all
+of the code compiled (if you only get errors printed to the console while using
+this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
+your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
+views the SelectionDAG output from the Select phase and input to the Scheduler
+phase.
+</p>
</div>
<!-- _______________________________________________________________________ -->
to the SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM
add turns into an SDNode add while a geteelementptr is expanded into the obvious
arithmetic). This pass requires target-specific hooks to lower calls and
-returns, varargs, etc. For these features, the TargetLowering interface is
+returns, varargs, etc. For these features, the <a
+href="#targetlowering">TargetLowering</a> interface is
used.
</p>
<ol>
<li><p>Convert values of unsupported types to values of supported types.</p>
- <p>There are two main ways of doing this: promoting a small type to a larger
- type (e.g. f32 -> f64, or i16 -> i32), and breaking up large
- integer types
- to smaller ones (e.g. implementing i64 with i32 operations where
- possible). Type conversions can insert sign and zero extensions as
+ <p>There are two main ways of doing this: converting small types to
+ larger types ("promoting"), and breaking up large integer types
+ into smaller ones ("expanding"). For example, a target might require
+ that all f32 values are promoted to f64 and that all i1/i8/i16 values
+ are promoted to i32. The same target might require that all i64 values
+ be expanded into i32 values. These changes can insert sign and zero
+ extensions as
needed to make sure that the final code has the same behavior as the
input.</p>
+ <p>A target implementation tells the legalizer which types are supported
+ (and which register class to use for them) by calling the
+ "addRegisterClass" method in its TargetLowering constructor.</p>
</li>
-<li><p>Eliminate operations that are not supported by the target in a supported
- type.</p>
- <p>Targets often have wierd constraints, such as not supporting every
+<li><p>Eliminate operations that are not supported by the target.</p>
+ <p>Targets often have weird constraints, such as not supporting every
operation on every supported datatype (e.g. X86 does not support byte
- conditional moves). Legalize takes care of either open-coding another
- sequence of operations to emulate the operation (this is known as
- expansion), promoting to a larger type that supports the operation
+ conditional moves and PowerPC does not support sign-extending loads from
+ a 16-bit memory location). Legalize takes care by open-coding
+ another sequence of operations to emulate the operation ("expansion"), by
+ promoting to a larger type that supports the operation
(promotion), or using a target-specific hook to implement the
- legalization.</p>
+ legalization (custom).</p>
+ <p>A target implementation tells the legalizer which operations are not
+ supported (and which of the above three actions to take) by calling the
+ "setOperationAction" method in its TargetLowering constructor.</p>
</li>
</ol>
<p>
-Instead of using a Legalize pass, we could require that every target-specific
-<a href="#selectiondag_optimize">selector</a> supports and expands every
-operator and type even if they are not supported and may require many
-instructions to implement (in fact, this is the approach taken by the
-"simple" selectors). However, using a Legalize pass allows all of the
-cannonicalization patterns to be shared across targets which makes it very
+Prior to the existance of the Legalize pass, we required that every
+target <a href="#selectiondag_optimize">selector</a> supported and handled every
+operator and type even if they are not natively supported. The introduction of
+the Legalize phase allows all of the
+cannonicalization patterns to be shared across targets, and makes it very
easy to optimize the cannonicalized code because it is still in the form of
a DAG.
</p>
of the pass allows the initial code to be cleaned up (e.g. performing
optimizations that depend on knowing that the operators have restricted type
inputs). The second run of the pass cleans up the messy code generated by the
-Legalize pass, allowing Legalize to be very simple since it can ignore many
-special cases.
+Legalize pass, which allows Legalize to be very simple (it can focus on making
+code legal instead of focusing on generating <i>good</i> and legal code).
</p>
<p>
<div class="doc_text">
<p>The Select phase is the bulk of the target-specific code for instruction
-selection. This phase takes a legal SelectionDAG as input, and does simple
-pattern matching on the DAG to generate code. In time, the Select phase will
-be automatically generated from the target's InstrInfo.td file, which is why we
-want to make the Select phase as simple and mechanical as possible.</p>
+selection. This phase takes a legal SelectionDAG as input,
+pattern matches the instructions supported by the target to this DAG, and
+produces a new DAG of target code. For example, consider the following LLVM
+fragment:</p>
+
+<pre>
+ %t1 = add float %W, %X
+ %t2 = mul float %t1, %Y
+ %t3 = add float %t2, %Z
+</pre>
+
+<p>This LLVM code corresponds to a SelectionDAG that looks basically like this:
+</p>
+
+<pre>
+ (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
+</pre>
+
+<p>If a target supports floating point multiply-and-add (FMA) operations, one
+of the adds can be merged with the multiply. On the PowerPC, for example, the
+output of the instruction selector might look like this DAG:</p>
+
+<pre>
+ (FMADDS (FADDS W, X), Y, Z)
+</pre>
+
+<p>
+The FMADDS instruction is a ternary instruction that multiplies its first two
+operands and adds the third (as single-precision floating-point numbers). The
+FADDS instruction is a simple binary single-precision add instruction. To
+perform this pattern match, the PowerPC backend includes the following
+instruction definitions:
+</p>
+
+<pre>
+def FMADDS : AForm_1<59, 29,
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+ "fmadds $FRT, $FRA, $FRC, $FRB",
+ [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
+ F4RC:$FRB))</b>]>;
+def FADDS : AForm_2<59, 21,
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
+ "fadds $FRT, $FRA, $FRB",
+ [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]>;
+</pre>
+
+<p>The portion of the instruction definition in bold indicates the pattern used
+to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
+are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
+"<tt>F4RC</tt>" is the register class of the input and result values.<p>
+
+<p>The TableGen DAG instruction selector generator reads the instruction
+patterns in the .td and automatically builds parts of the pattern matching code
+for your target. It has the following strengths:</p>
+
+<ul>
+<li>At compiler-compiler time, it analyzes your instruction patterns and tells
+ you if your patterns make sense or not.</li>
+<li>It can handle arbitrary constraints on operands for the pattern match. In
+ particular, it is straight-forward to say things like "match any immediate
+ that is a 13-bit sign-extended value". For examples, see the
+ <tt>immSExt16</tt> and related tblgen classes in the PowerPC backend.</li>
+<li>It knows several important identities for the patterns defined. For
+ example, it knows that addition is commutative, so it allows the
+ <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
+ well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
+ to specially handle this case.</li>
+<li>It has a full-featured type-inferencing system. In particular, you should
+ rarely have to explicitly tell the system what type parts of your patterns
+ are. In the FMADDS case above, we didn't have to tell tblgen that all of
+ the nodes in the pattern are of type 'f32'. It was able to infer and
+ propagate this knowledge from the fact that F4RC has type 'f32'.</li>
+<li>Targets can define their own (and rely on built-in) "pattern fragments".
+ Pattern fragments are chunks of reusable patterns that get inlined into your
+ patterns during compiler-compiler time. For example, the integer "(not x)"
+ operation is actually defined as a pattern fragment that expands as
+ "(xor x, -1)", since the SelectionDAG does not have a native 'not'
+ operation. Targets can define their own short-hand fragments as they see
+ fit. See the definition of 'not' and 'ineg' for examples.</li>
+<li>In addition to instructions, targets can specify arbitrary patterns that
+ map to one or more instructions, using the 'Pat' class. For example,
+ the PowerPC has no way to load an arbitrary integer immediate into a
+ register in one instruction. To tell tblgen how to do this, it defines:
+
+ <pre>
+ // Arbitrary immediate support. Implement in terms of LIS/ORI.
+ def : Pat<(i32 imm:$imm),
+ (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
+ </pre>
+
+ If none of the single-instruction patterns for loading an immediate into a
+ register match, this will be used. This rule says "match an arbitrary i32
+ immediate, turning it into an ORI ('or a 16-bit immediate') and an LIS
+ ('load 16-bit immediate, where the immediate is shifted to the left 16
+ bits') instruction". To make this work, the LO16/HI16 node transformations
+ are used to manipulate the input immediate (in this case, take the high or
+ low 16-bits of the immediate).
+ </li>
+<li>While the system does automate a lot, it still allows you to write custom
+ C++ code to match special cases, in case there is something that is hard
+ to express.</li>
+</ul>
+
+<p>
+While it has many strengths, the system currently has some limitations,
+primarily because it is a work in progress and is not yet finished:
+</p>
+
+<ul>
+<li>Overall, there is no way to define or match SelectionDAG nodes that define
+ multiple values (e.g. ADD_PARTS, LOAD, CALL, etc). This is the biggest
+ reason that you currently still <i>have to</i> write custom C++ code for
+ your instruction selector.</li>
+<li>There is no great way to support match complex addressing modes yet. In the
+ future, we will extend pattern fragments to allow them to define multiple
+ values (e.g. the four operands of the <a href="#x86_memory">X86 addressing
+ mode</a>). In addition, we'll extend fragments so that a fragment can match
+ multiple different patterns.</li>
+<li>We don't automatically infer flags like isStore/isLoad yet.</li>
+<li>We don't automatically generate the set of supported registers and
+ operations for the <a href="#"selectiondag_legalize>Legalizer</a> yet.</li>
+<li>We don't have a way of tying in custom legalized nodes yet.</li>
+</ul>
+
+<p>Despite these limitations, the instruction selector generator is still quite
+useful for most of the binary and logical operations in typical instruction
+sets. If you run into any problems or can't figure out how to do something,
+please let Chris know!</p>
</div>
<!-- _______________________________________________________________________ -->
<div class="doc_subsubsection">
- <a name="selectiondag_sched">SelectionDAG Scheduling and Emission Phase</a>
+ <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
</div>
<div class="doc_text">
Selection DAG is destroyed.
</p>
+<p>Note that this phase is logically separate from the instruction selection
+phase, but is tied to it closely in the code because it operates on
+SelectionDAGs.</p>
+
</div>
<!-- _______________________________________________________________________ -->
<div class="doc_text"><p>To Be Written</p></div>
<!-- ======================================================================= -->
<div class="doc_subsection">
- <a name="codemission">Code Emission</a>
+ <a name="codeemit">Code Emission</a>
+</div>
+
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="codeemit_asm">Generating Assembly Code</a>
+</div>
+
+<div class="doc_text">
+
+</div>
+
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="codeemit_bin">Generating Binary Machine Code</a>
</div>
+<div class="doc_text">
+ <p>For the JIT or .o file writer</p>
+</div>
+
+
<!-- *********************************************************************** -->
<div class="doc_section">
- <a name="targetimpls">Target description implementations</a>
+ <a name="targetimpls">Target-specific Implementation Notes</a>
</div>
<!-- *********************************************************************** -->
<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
-<li><b>i686-apple-darwin*</b> - Apple Darwin</li>
+<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
</ul>
</div>
src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /></a>
<a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
- <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
+ <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
Last modified: $Date$
</address>
projects / oota-llvm.git / blobdiff