<ul>
<li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
<li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
+ <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
<li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
<li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
<li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
</ul>
</li>
<li><a href="#codegendesc">Machine code description classes</a>
+ <ul>
+ <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
+ </ul>
</li>
<li><a href="#codegenalgs">Target-independent code generation algorithms</a>
+ <ul>
+ <li><a href="#instselect">Instruction Selection</a>
+ <ul>
+ <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
+ <li><a href="#selectiondag_process">SelectionDAG Code Generation
+ Process</a></li>
+ <li><a href="#selectiondag_build">Initial SelectionDAG
+ Construction</a></li>
+ <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
+ <li><a href="#selectiondag_optimize">SelectionDAG Optimization
+ Phase</a></li>
+ <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
+ <li><a href="#selectiondag_future">Future directions for the
+ SelectionDAG</a></li>
+ </ul></li>
+ </ul>
</li>
<li><a href="#targetimpls">Target description implementations</a>
<ul>
-
<li><a href="#x86">The X86 backend</a></li>
+ <li><a href="#x86">The X86 backend</a></li>
</ul>
</li>
suite of reusable components for translating the LLVM internal representation to
the machine code for a specified target -- either in assembly form (suitable for
a static compiler) or in binary machine code format (usable for a JIT compiler).
-The LLVM target-independent code generator consists of four main components:</p>
+The LLVM target-independent code generator consists of five main components:</p>
<ol>
<li><a href="#targetdesc">Abstract target description</a> interfaces which
-capture improtant properties about various aspects of the machine independently
+capture important properties about various aspects of the machine, independently
of how they will be used. These interfaces are defined in
<tt>include/llvm/Target/</tt>.</li>
<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
-generator for a target. These classes are intended to be abstract enough to
+generated for a target. These classes are intended to be abstract enough to
represent the machine code for <i>any</i> target machine. These classes are
defined in <tt>include/llvm/CodeGen/</tt>.</li>
target-specific passes, to build complete code generators for a specific target.
Target descriptions live in <tt>lib/Target/</tt>.</li>
+<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
+completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
+interface for target-specific issues. The code for the target-independent
+JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
+
</ol>
<p>
different pieces of this will be useful to you. In any case, you should be
familiar with the <a href="#targetdesc">target description</a> and <a
href="#codegendesc">machine code representation</a> classes. If you want to add
-a backend for a new target, you will need <a href="#targetimpls">implement the
-targe description</a> classes for your new target and understand the <a
+a backend for a new target, you will need
to <a href="#targetimpls">implement the
+targe
t description</a> classes for your new target and understand the <a
href="LangRef.html">LLVM code representation</a>. If you are interested in
implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
should only depend on the target-description and machine code representation
code generator and the set of reusable components that can be used to build
target-specific backends. The two most important interfaces (<a
href="#targetmachine"><tt>TargetMachine</tt></a> and <a
-href="#targetdata"><tt>TargetData</tt></a> classes) are the only ones that are
+href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
required to be defined for a backend to fit into the LLVM system, but the others
must be defined if the reusable code generator components are going to be
used.</p>
code generator like this is a (purely hypothetical) backend that converts LLVM
to the GCC RTL form and uses GCC to emit machine code for a target.</p>
-<p>The other implication of this design is that it is possible to design and
+<p>This design also implies that it is possible to design and
implement radically different code generators in the LLVM system that do not
make use of any of the built-in components. Doing so is not recommended at all,
but could be required for radically different targets that do not fit into the
LLVM machine description model: programmable FPGAs for example.</p>
+
+<p><b>Important Note:</b> For historical reasons, the LLVM SparcV9 code
+generator uses almost entirely different code paths than described in this
+document. For this reason, there are some deprecated interfaces (such as
+<tt>TargetRegInfo</tt> and <tt>TargetSchedInfo</tt>), which are only used by the
+V9 backend and should not be used by any other targets. Also, all code in the
+<tt>lib/Target/SparcV9</tt> directory and subdirectories should be considered
+deprecated, and should not be used as the basis for future code generator work.
+The SparcV9 backend is slowly being merged into the rest of the
+target-independent code generators, but this is a low-priority process with no
+predictable completion date.</p>
+
</div>
<!-- ======================================================================= -->
<div class="doc_text">
-<p>The LLVM target-indendent code generator is designed to support efficient and
+<p>The LLVM target-independent code generator is designed to support efficient and
quality code generation for standard register-based microprocessors. Code
generation in this model is divided into the following stages:</p>
<ol>
-<li><b>Instruction Selection</b> - Determining a efficient implementation of the
-input LLVM code in the target instruction set. This stage produces the initial
-code for the program in the target instruction set the makes use of virtual
-registers in SSA form and physical registers that represent any required
-register assignments due to target constraints or calling conventions.</li>
-
-<li><b>SSA-based Machine Code Optimizations</b> - This (optional) stage consists
-of a series of machine-code optimizations that operate on the SSA-form produced
-by the instruction selector. Optimizations like modulo-scheduling, normal
-scheduling, or peephole optimization work here.</li>
-
-<li><b>Register Allocation</b> - The target code is transformed from an infinite
-virtual register file in SSA form to the concrete register file used by the
-target. This phase introduces spill code and eliminates all virtual register
-references from the program.</li>
-
-<li><b>Prolog/Epilog Code Insertion</b> - Once the machine code has been
-generated for the function and the amount of stack space required is known (used
-for LLVM alloca's and spill slots), the prolog and epilog code for the function
-can be inserted and "abstract stack location references" can be eliminated.
-This stage is responsible for implementing optimizations like frame-pointer
-elimination and stack packing.</li>
-
-<li><b>Late Machine Code Optimizations</b> - Optimizations that operate on
-"final" machine code can go here, such as spill code scheduling and peephole
-optimizations.</li>
-
-<li><b>Code Emission</b> - The final stage actually outputs the machine code for
-the current function, either in the target assembler format or in machine
-code.</li>
+<li><b><a href="#instselect">Instruction Selection</a></b> - Determining an
+efficient implementation of the input LLVM code in the target instruction set.
+This stage produces the initial code for the program in the target instruction
+set, then makes use of virtual registers in SSA form and physical registers that
+represent any required register assignments due to target constraints or calling
+conventions.</li>
+
+<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
+optional stage consists of a series of machine-code optimizations that
+operate on the SSA-form produced by the instruction selector. Optimizations
+like modulo-scheduling, normal scheduling, or peephole optimization work here.
+</li>
+
+<li><b><a name="#regalloc">Register Allocation</a></b> - The
+target code is transformed from an infinite virtual register file in SSA form
+to the concrete register file used by the target. This phase introduces spill
+code and eliminates all virtual register references from the program.</li>
+
+<li><b><a name="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
+machine code has been generated for the function and the amount of stack space
+required is known (used for LLVM alloca's and spill slots), the prolog and
+epilog code for the function can be inserted and "abstract stack location
+references" can be eliminated. This stage is responsible for implementing
+optimizations like frame-pointer elimination and stack packing.</li>
+
+<li><b><a name="latemco">Late Machine Code Optimizations</a></b> - Optimizations
+that operate on "final" machine code can go here, such as spill code scheduling
+and peephole optimizations.</li>
+
+<li><b><a name="codemission">Code Emission</a></b> - The final stage actually
+puts out the code for the current function, either in the target assembler
+format or in machine code.</li>
</ol>
<p>
The code generator is based on the assumption that the instruction selector will
use an optimal pattern matching selector to create high-quality sequences of
-native code. Alternative code generator designs based on pattern expansion and
-aggressive iterative peephole optimization are much slower. This design is
-designed to permit efficient compilation (important for JIT environments) and
-aggressive optimization (used when generate code offline) by allowing components
-of varying levels of sophisication to be used for any step of compilation.</p>
+native instructions. Alternative code generator designs based on pattern
+expansion and
+aggressive iterative peephole optimization are much slower. This design
+permits efficient compilation (important for JIT environments) and
+aggressive optimization (used when generating code offline) by allowing
+components of varying levels of sophistication to be used for any step of
+compilation.</p>
<p>
In addition to these stages, target implementations can insert arbitrary
<div class="doc_text">
-<p>The target description classes require a detailed descriptions of the target
+<p>The target description classes require a detailed description of the target
architecture. These target descriptions often have a large amount of common
-information (e.g., an add instruction is almost identical to a sub instruction).
+information (e.g., an <tt>add</tt> instruction is almost identical to a
+<tt>sub</tt> instruction).
In order to allow the maximum amount of commonality to be factored out, the LLVM
code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
-allow
+describe big chunks of the target machine, which allows the use of
+domain-specific and target-specific abstractions to reduce the amount of
+repetition.
</p>
</div>
<p>The LLVM target description classes (which are located in the
<tt>include/llvm/Target</tt> directory) provide an abstract description of the
-target machine, independent of any particular client. These classes are
-designed to capture the <i>abstract</i> properties of the target (such as what
-instruction and registers it has), and do not incorporate any particular pieces
-of code generation algorithms (these interfaces do not take interference graphs
-as inputs or other algorithm-specific data structures).</p>
+target machine; independent of any particular client. These classes are
+designed to capture the <i>abstract</i> properties of the target (such as the
+instructions and registers it has), and do not incorporate any particular pieces
+of code generation algorithms. These interfaces do not take interference graphs
+as inputs or other algorithm-specific data structures.</p>
<p>All of the target description classes (except the <tt><a
href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
the concrete target implementation, and have virtual methods implemented. To
-get to these implementations, <tt><a
+get to these implementations,
the <tt><a
href="#targetmachine">TargetMachine</a></tt> class provides accessors that
should be implemented by the target.</p>
<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
access the target-specific implementations of the various target description
-classes (with the <tt>getInstrInfo</tt>, <tt>getRegisterInfo</tt>,
-<tt>getFrameInfo</tt>, ... methods). This class is designed to be subclassed by
+classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
+<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
+designed to be specialized by
a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
implements the various virtual methods. The only required target description
class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
<div class="doc_text">
<p>The <tt>TargetData</tt> class is the only required target description class,
-and it is the only class that is not extensible (it cannot be derived from). It
-specifies information about how the target lays out memory for structures, the
-alignment requirements for various data types, the size of pointers in the
-target, and whether the target is little- or big-endian.</p>
+and it is the only class that is not extensible. You cannot derived a new
+class from it. <tt>TargetData</tt> specifies information about how the target
+lays out memory for structures, the alignment requirements for various data
+types, the size of pointers in the target, and whether the target is
+little-endian or big-endian.</p>
</div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
+</div>
+
+<div class="doc_text">
+
+<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
+selectors primarily to describe how LLVM code should be lowered to SelectionDAG
+operations. Among other things, this class indicates:
+<ul><li>an initial register class to use for various ValueTypes,</li>
+ <li>which operations are natively supported by the target machine,</li>
+ <li>the return type of setcc operations, and</li>
+ <li>the type to use for shift amounts, etc</li>.
+</ol></p>
+
+</div>
+
+
+
+
<!-- ======================================================================= -->
<div class="doc_subsection">
</div>
<!-- *********************************************************************** -->
+<div class="doc_text">
+
+<p>
+At the high-level, LLVM code is translated to a machine specific representation
+formed out of MachineFunction, MachineBasicBlock, and <a
+href="#machineinstr"><tt>MachineInstr</tt></a> instances
+(defined in include/llvm/CodeGen). This representation is completely target
+agnostic, representing instructions in their most abstract form: an opcode and a
+series of operands. This representation is designed to support both SSA
+representation for machine code, as well as a register allocated, non-SSA form.
+</p>
+
+</div>
+
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
+</div>
+
+<div class="doc_text">
+
+<p>Target machine instructions are represented as instances of the
+<tt>MachineInstr</tt> class. This class is an extremely abstract way of
+representing machine instructions. In particular, it only keeps track of
+an opcode number and a set of operands.</p>
+
+<p>The opcode number is a simple unsigned number that only has meaning to a
+specific backend. All of the instructions for a target should be defined in
+the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
+are auto-generated from this description. The <tt>MachineInstr</tt> class does
+not have any information about how to interpret the instruction (i.e., what the
+semantics of the instruction are): for that you must refer to the
+<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
+
+<p>The operands of a machine instruction can be of several different types:
+they can be a register reference, constant integer, basic block reference, etc.
+In addition, a machine operand should be marked as a def or a use of the value
+(though only registers are allowed to be defs).</p>
+
+<p>By convention, the LLVM code generator orders instruction operands so that
+all register definitions come before the register uses, even on architectures
+that are normally printed in other orders. For example, the SPARC add
+instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
+and stores the result into the "%i3" register. In the LLVM code generator,
+the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
+first.</p>
+
+<p>Keeping destination (definition) operands at the beginning of the operand
+list has several advantages. In particular, the debugging printer will print
+the instruction like this:</p>
+
+<pre>
+ %r3 = add %i1, %i2
+</pre>
+
+<p>If the first operand is a def, and it is also easier to <a
+href="#buildmi">create instructions</a> whose only def is the first
+operand.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
+</div>
+
+<div class="doc_text">
+
+<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
+located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
+<tt>BuildMI</tt> functions make it easy to build arbitrary machine
+instructions. Usage of the <tt>BuildMI</tt> functions look like this:
+</p>
+
+<pre>
+ // Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
+ // instruction. The '1' specifies how many operands will be added.
+ MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
+
+ // Create the same instr, but insert it at the end of a basic block.
+ MachineBasicBlock &MBB = ...
+ BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
+
+ // Create the same instr, but insert it before a specified iterator point.
+ MachineBasicBlock::iterator MBBI = ...
+ BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
+
+ // Create a 'cmp Reg, 0' instruction, no destination reg.
+ MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
+ // Create an 'sahf' instruction which takes no operands and stores nothing.
+ MI = BuildMI(X86::SAHF, 0);
+
+ // Create a self looping branch instruction.
+ BuildMI(MBB, X86::JNE, 1).addMBB(&MBB);
+</pre>
+
+<p>
+The key thing to remember with the <tt>BuildMI</tt> functions is that you have
+to specify the number of operands that the machine instruction will take. This
+allows for efficient memory allocation. You also need to specify if operands
+default to be uses of values, not definitions. If you need to add a definition
+operand (other than the optional destination register), you must explicitly
+mark it as such.
+</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="fixedregs">Fixed (preassigned) registers</a>
+</div>
+
+<div class="doc_text">
+
+<p>One important issue that the code generator needs to be aware of is the
+presence of fixed registers. In particular, there are often places in the
+instruction stream where the register allocator <em>must</em> arrange for a
+particular value to be in a particular register. This can occur due to
+limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
+with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
+conventions. In any case, the instruction selector should emit code that
+copies a virtual register into or out of a physical register when needed.</p>
+
+<p>For example, consider this simple LLVM example:</p>
+
+<pre>
+ int %test(int %X, int %Y) {
+ %Z = div int %X, %Y
+ ret int %Z
+ }
+</pre>
+
+<p>The X86 instruction selector produces this machine code for the div
+and ret (use
+"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
+
+<pre>
+ ;; Start of div
+ %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
+ %reg1027 = sar %reg1024, 31
+ %EDX = mov %reg1027 ;; Sign extend X into EDX
+ idiv %reg1025 ;; Divide by Y (in reg1025)
+ %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
+
+ ;; Start of ret
+ %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
+ ret
+</pre>
+
+<p>By the end of code generation, the register allocator has coalesced
+the registers and deleted the resultant identity moves, producing the
+following code:</p>
+
+<pre>
+ ;; X is in EAX, Y is in ECX
+ mov %EAX, %EDX
+ sar %EDX, 31
+ idiv %ECX
+ ret
+</pre>
+
+<p>This approach is extremely general (if it can handle the X86 architecture,
+it can handle anything!) and allows all of the target specific
+knowledge about the instruction stream to be isolated in the instruction
+selector. Note that physical registers should have a short lifetime for good
+code generation, and all physical registers are assumed dead on entry and
+exit of basic blocks (before register allocation). Thus if you need a value
+to be live across basic block boundaries, it <em>must</em> live in a virtual
+register.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="ssa">Machine code SSA form</a>
+</div>
+<div class="doc_text">
+
+<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
+are maintained in SSA-form until register allocation happens. For the most
+part, this is trivially simple since LLVM is already in SSA form: LLVM PHI nodes
+become machine code PHI nodes, and virtual registers are only allowed to have a
+single definition.</p>
+
+<p>After register allocation, machine code is no longer in SSA-form, as there
+are no virtual registers left in the code.</p>
+
+</div>
+
+<!-- *********************************************************************** -->
+<div class="doc_section">
+ <a name="codegenalgs">Target-independent code generation algorithms</a>
+</div>
+<!-- *********************************************************************** -->
+
+<div class="doc_text">
+
+<p>This section documents the phases described in the <a
+href="high-level-design">high-level design of the code generator</a>. It
+explains how they work and some of the rationale behind their design.</p>
+
+</div>
+
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="instselect">Instruction Selection</a>
+</div>
+
+<div class="doc_text">
+<p>
+Instruction Selection is the process of translating LLVM code presented to the
+code generator into target-specific machine instructions. There are several
+well-known ways to do this in the literature. In LLVM there are two main forms:
+the old-style 'simple' instruction selector (which effectively peephole selects
+each LLVM instruction into a series of machine instructions), and the new
+SelectionDAG based instruction selector.
+</p>
+
+<p>The 'simple' instruction selectors are tedious to write, require a lot of
+boiler plate code, and are difficult to get correct. Additionally, any
+optimizations written for a simple instruction selector cannot be used by other
+targets. For this reason, LLVM is moving to a new SelectionDAG based
+instruction selector, which is described in this section. If you are starting a
+new port, we recommend that you write the instruction selector using the
+SelectionDAG infrastructure.</p>
+
+<p>In time, most of the target-specific code for instruction selection will be
+auto-generated from the target description (<tt>*.td</tt>) files. For now,
+however, the <a href="#selectiondag_select">Select Phase</a> must still be
+written by hand.</p>
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
+</div>
+
+<div class="doc_text">
+
+<p>
+The SelectionDAG provides an abstraction for code representation in a way that
+is amenable to instruction selection using automatic techniques
+(e.g. dynamic-programming based optimal pattern matching selectors), It is also
+well suited to other phases of code generation; in particular, instruction scheduling. Additionally, the SelectionDAG provides a host representation where a
+large variety of very-low-level (but target-independent)
+<a href="#selectiondag_optimize">optimizations</a> may be
+performed: ones which require extensive information about the instructions
+efficiently supported by the target.
+</p>
+
+<p>
+The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
+<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
+operation code (Opcode) that indicates what operation the node performs.
+The various operation node types are described at the top of the
+<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file. Depending on the
+operation, nodes may contain additional information (e.g. the condition code
+for a SETCC node) contained in a derived class.</p>
+
+<p>Although most operations define a single value, each node in the graph may
+define multiple values. For example, a combined div/rem operation will define
+both the dividend and the remainder. Many other situations require multiple
+values as well. Each node also has some number of operands, which are edges
+to the node defining the used value. Because nodes may define multiple values,
+edges are represented by instances of the <tt>SDOperand</tt> class, which is
+a <SDNode, unsigned> pair, indicating the node and result
+value being used, respectively. Each value produced by an SDNode has an
+associated MVT::ValueType, indicating what type the value is.
+</p>
+
+<p>
+SelectionDAGs contain two different kinds of values: those that represent data
+flow and those that represent control flow dependencies. Data values are simple
+edges with an integer or floating point value type. Control edges are
+represented as "chain" edges which are of type MVT::Other. These edges provide
+an ordering between nodes that have side effects (such as
+loads/stores/calls/return/etc). All nodes that have side effects should take a
+token chain as input and produce a new one as output. By convention, token
+chain inputs are always operand #0, and chain results are always the last
+value produced by an operation.</p>
+
+<p>
+A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
+always a marker node with an Opcode of ISD::TokenFactor. The Root node is the
+final side-effecting node in the token chain. For example, in a single basic
+block function, this would be the return node.
+</p>
+
+<p>
+One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal"
+DAG. A legal DAG for a target is one that only uses supported operations and
+supported types. On PowerPC, for example, a DAG with any values of i1, i8, i16,
+or i64 type would be illegal. The <a href="#selectiondag_legalize">legalize</a>
+phase is responsible for turning an illegal DAG into a legal DAG.
+</p>
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
+</div>
+
+<div class="doc_text">
+
+<p>
+SelectionDAG-based instruction selection consists of the following steps:
+</p>
+
+<ol>
+<li><a href="#selectiondag_build">Build initial DAG</a> - This stage performs
+ a simple translation from the input LLVM code to an illegal SelectionDAG.
+ </li>
+<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
+ performs simple optimizations on the SelectionDAG to simplify it and
+ recognize meta instructions (like rotates and div/rem pairs) for
+ targets that support these meta operations. This makes the resultant code
+ more efficient and the 'select instructions from DAG' phase (below) simpler.
+</li>
+<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
+ converts the illegal SelectionDAG to a legal SelectionDAG, by eliminating
+ unsupported operations and data types.</li>
+<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
+ second run of the SelectionDAG optimized the newly legalized DAG, to
+ eliminate inefficiencies introduced by legalization.</li>
+<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
+ the target instruction selector matches the DAG operations to target
+ instructions, emitting them and building the MachineFunction being
+ compiled.</li>
+</ol>
+
+<p>After all of these steps are complete, the SelectionDAG is destroyed and the
+rest of the code generation passes are run.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="selectiondag_build">Initial SelectionDAG Construction</a>
+</div>
+
+<div class="doc_text">
+
+<p>
+The initial SelectionDAG is naively peephole expanded from the LLVM input by
+the <tt>SelectionDAGLowering</tt> class in the SelectionDAGISel.cpp file. The
+intent of this pass is to expose as much low-level, target-specific details
+to the SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM
+add turns into an SDNode add while a geteelementptr is expanded into the obvious
+arithmetic). This pass requires target-specific hooks to lower calls and
+returns, varargs, etc. For these features, the TargetLowering interface is
+used.
+</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
+</div>
+
+<div class="doc_text">
+
+<p>The Legalize phase is in charge of converting a DAG to only use the types and
+operations that are natively supported by the target. This involves two major
+tasks:</p>
+
+<ol>
+<li><p>Convert values of unsupported types to values of supported types.</p>
+ <p>There are two main ways of doing this: promoting a small type to a larger
+ type (e.g. f32 -> f64, or i16 -> i32), and demoting larg integer types
+ to smaller ones (e.g. implementing i64 with i32 operations where
+ possible). Type conversions can insert sign and zero extensions as
+ needed to make sure that the final code has the same behavior as the
+ input.</p>
+</li>
+
+<li><p>Eliminate operations that are not supported by the target in a supported
+ type.</p>
+ <p>Targets often have wierd constraints, such as not supporting every
+ operation on every supported datatype (e.g. X86 does not support byte
+ conditional moves). Legalize takes care of either open-coding another
+ sequence of operations to emulate the operation (this is known as
+ expansion), promoting to a larger type that supports the operation
+ (promotion), or using a target-specific hook to implement the
+ legalization.</p>
+</li>
+</ol>
+
+<p>
+Instead of using a Legalize pass, we could require that every target-specific
+<a href="#selectiondag_optimize">selector</a> supports and expands every
+operator and type even if they are not supported and may require many
+instructions to implement (in fact, this is the approach taken by the
+"simple" selectors). However, using a Legalize pass allows all of the
+cannonicalization patterns to be shared across targets which makes it very
+easy to optimize the cannonicalized code because it is still in the form of
+a DAG.
+</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="selectiondag_optimize">SelectionDAG Optimization Phase</a>
+</div>
+
+<div class="doc_text">
+
+<p>
+The SelectionDAG optimization phase is run twice for code generation: once
+immediately after the DAG is built and once after legalization. The first run
+of the pass allows the initial code to be cleaned up (e.g. performing
+optimizations that depend on knowing that the operators have restricted type
+inputs). The second run of the pass cleans up the messy code generated by the
+Legalize pass, allowing Legalize to be very simple since it can ignore many
+special cases.
+</p>
+
+<p>
+One important class of optimizations that this pass will do in the future is
+optimizing inserted sign and zero extension instructions. Here are some good
+papers on the subject:</p>
+
+<p>
+"<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
+integer arithmetic</a>"<br>
+Kevin Redwine and Norman Ramsey<br>
+International Conference on Compiler Construction (CC) 2004
+</p>
+
+
+<p>
+ "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
+ sign extension elimination</a>"<br>
+ Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
+ Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
+ and Implementation.
+</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="selectiondag_select">SelectionDAG Select Phase</a>
+</div>
+
+<div class="doc_text">
+
+<p>The Select phase is the bulk of the target-specific code for instruction
+selection. This phase takes a legal SelectionDAG as input, and does simple
+pattern matching on the DAG to generate code. In time, the Select phase will
+be automatically generated from the target's InstrInfo.td file, which is why we
+want to make the Select phase as simple and mechanical as possible.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="selectiondag_future">Future directions for the SelectionDAG</a>
+</div>
+
+<div class="doc_text">
+
+<ol>
+<li>Optional whole-function selection.</li>
+<li>Select is a graph translation phase.</li>
+<li>Place the machine instructions resulting from Select according to register
+pressure or a schedule.</li>
+<li>DAG Scheduling.</li>
+<li>Auto-generate the Select phase from the target description (*.td) files.
+</li>
+</ol>
+
+</div>
+
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="ssamco">SSA-based Machine Code Optimizations</a>
+</div>
+<div class="doc_text"><p>To Be Written</p></div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="regalloc">Register Allocation</a>
+</div>
+<div class="doc_text"><p>To Be Written</p></div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="proepicode">Prolog/Epilog Code Insertion</a>
+</div>
+<div class="doc_text"><p>To Be Written</p></div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="latemco">Late Machine Code Optimizations</a>
+</div>
+<div class="doc_text"><p>To Be Written</p></div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="codemission">Code Emission</a>
+</div>
+
+<!-- *********************************************************************** -->
+<div class="doc_section">
+ <a name="targetimpls">Target description implementations</a>
+</div>
+<!-- *********************************************************************** -->
+
+<div class="doc_text">
+
+<p>This section of the document explains features or design decisions that
+are specific to the code generator for a particular target.</p>
+
+</div>
+
+
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="x86">The X86 backend</a>
+</div>
+
+<div class="doc_text">
+
+<p>
+The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
+code generator currently targets a generic P6-like processor. As such, it
+produces a few P6-and-above instructions (like conditional moves), but it does
+not make use of newer features like MMX or SSE. In the future, the X86 backend
+will have sub-target support added for specific processor families and
+implementations.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
+</div>
+
+<div class="doc_text">
+
+<p>The x86 has a very flexible way of accessing memory. It is capable of
+forming memory addresses of the following expression directly in integer
+instructions (which use ModR/M addressing):</p>
+
+<pre>
+ Base+[1,2,4,8]*IndexReg+Disp32
+</pre>
+
+<p>In order to represent this, LLVM tracks no less than 4 operands for each
+memory operand of this form. This means that the "load" form of 'mov' has the
+following <tt>MachineOperand</tt>s in this order:</p>
+
+<pre>
+Index: 0 | 1 2 3 4
+Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
+OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
+</pre>
+
+<p>Stores, and all other instructions, treat the four memory operands in the
+same way, in the same order.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="x86_names">Instruction naming</a>
+</div>
+
+<div class="doc_text">
+
+<p>
+An instruction name consists of the base name, a default operand size, and a
+a character per operand with an optional special size. For example:</p>
+
+<p>
+<tt>ADD8rr</tt> -> add, 8-bit register, 8-bit register<br>
+<tt>IMUL16rmi</tt> -> imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
+<tt>IMUL16rmi8</tt> -> imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
+<tt>MOVSX32rm16</tt> -> movsx, 32-bit register, 16-bit memory
+</p>
+
+</div>
<!-- *********************************************************************** -->
<hr>
projects / oota-llvm.git / blobdiff