ARM64: dts: rk3399-tb: limit emmc freq to 50MHz

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3399-tb.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-tb.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-tb.dtsi
index 80a6bdf0196565031a2a4559a9ac8187a1eda70c..68391d23e5c2f6281129e5c24b29a5d41dd7af44 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-tb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-tb.dtsi
@@ -114,6 +114,81 @@
                default-brightness-level = <200>;
                enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
        };
+
+       ext_gmac: external-gmac-clock {
+               compatible = "fixed-clock";
+               clock-frequency = <125000000>;
+               clock-output-names = "ext_gmac";
+               #clock-cells = <0>;
+       };
+
+       vcc_phy: vcc-phy-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc_phy";
+               regulator-always-on;
+               regulator-boot-on;
+       };
+
+       io-domains {
+               compatible = "rockchip,rk3399-io-voltage-domain";
+               rockchip,grf = <&grf>;
+
+               bt656-supply = <&vcc1v8_dvp>;
+               audio-supply = <&vcca1v8_codec>;
+               sdmmc-supply = <&vcc_sd>;
+               gpio1830-supply = <&vcc_3v0>;
+       };
+
+       pmu-io-domains {
+               compatible = "rockchip,rk3399-pmu-io-voltage-domain";
+               rockchip,grf = <&pmugrf>;
+
+               pmu1830-supply = <&vcc1v8_pmu>;
+       };
+};
+
+&sdmmc {
+       clock-frequency = <37500000>;
+       clock-freq-min-max = <400000 37500000>;
+       supports-sd;
+       bus-width = <4>;
+       cap-mmc-highspeed;
+       cap-sd-highspeed;
+       disable-wp;
+       num-slots = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+       status = "disabled";
+};
+
+&sdio0 {
+       clock-frequency = <37500000>;
+       clock-freq-min-max = <200000 37500000>;
+       supports-sdio;
+       bus-width = <4>;
+       disable-wp;
+       cap-sd-highspeed;
+       cap-sdio-irq;
+       keep-power-in-suspend;
+       //mmc-pwrseq = <&sdio_pwrseq>;
+       non-removable;
+       num-slots = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+       sd-uhs-sdr104;
+       status = "disabled";
+};
+
+&emmc_phy {
+       status = "okay";
+};
+
+&sdhci {
+       bus-width = <8>;
+       supports-emmc;
+       non-removable;
+       max-frequency = <50000000>;
+       status = "okay";
 };
 
 &i2s0 {
@@ -342,6 +417,62 @@
        status = "okay";
 };
 
+&usbdrd3_0 {
+       status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+       status = "okay";
+};
+
+&usbdrd3_1 {
+       status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+       status = "okay";
+};
+
 &pwm0 {
        status = "okay";
 };
+
+&cpu_l0 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+       cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+       cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+       cpu-supply = <&vdd_cpu_b>;
+};
+
+&gmac {
+       phy-supply = <&vcc_phy>;
+       phy-mode = "rgmii";
+       clock_in_out = "input";
+       snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
+       snps,reset-active-low;
+       snps,reset-delays-us = <0 10000 50000>;
+       assigned-clocks = <&cru SCLK_MAC>;
+       assigned-clock-parents = <&ext_gmac>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&rgmii_pins>;
+       tx_delay = <0x30>;
+       rx_delay = <0x10>;
+       status = "disabled";
+};