#include <linux/wakelock.h>\r
#include <linux/cdev.h>\r
#include <linux/of.h>\r
+#include <linux/of_platform.h>\r
#include <linux/rockchip/cpu.h>\r
#include <linux/rockchip/cru.h>\r
\r
#include <asm/cacheflush.h>\r
-#include <asm/uaccess.h>\r
+#include <linux/uaccess.h>\r
+#include <linux/rockchip/grf.h>\r
+\r
+#if defined(CONFIG_ION_ROCKCHIP)\r
+#include <linux/rockchip_ion.h>\r
+#endif\r
+\r
+#if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)\r
+#define CONFIG_VCODEC_MMU\r
+#endif\r
+\r
+#ifdef CONFIG_VCODEC_MMU\r
+#include <linux/rockchip-iovmm.h>\r
+#include <linux/dma-buf.h>\r
+#endif\r
\r
#ifdef CONFIG_DEBUG_FS\r
#include <linux/debugfs.h>\r
\r
#include "vcodec_service.h"\r
\r
-#define HEVC_TEST_ENABLE 0\r
+#define HEVC_TEST_ENABLE 0\r
#define HEVC_SIM_ENABLE 0\r
+#define VCODEC_CLOCK_ENABLE 1\r
\r
typedef enum {\r
VPU_DEC_ID_9190 = 0x6731,\r
VPU_ID_8270 = 0x8270,\r
VPU_ID_4831 = 0x4831,\r
- HEVC_ID = 0x6867,\r
+ HEVC_ID = 0x6867,\r
} VPU_HW_ID;\r
\r
typedef enum {\r
VPU_FREQ_266M,\r
VPU_FREQ_300M,\r
VPU_FREQ_400M,\r
+ VPU_FREQ_500M,\r
+ VPU_FREQ_600M,\r
VPU_FREQ_DEFAULT,\r
VPU_FREQ_BUT,\r
} VPU_FREQ;\r
unsigned long dec_io_size;\r
} VPU_HW_INFO_E;\r
\r
+struct extra_info_elem {\r
+ u32 index;\r
+ u32 offset;\r
+};\r
+\r
+#define EXTRA_INFO_MAGIC 0x4C4A46\r
+\r
+struct extra_info_for_iommu {\r
+ u32 magic;\r
+ u32 cnt;\r
+ struct extra_info_elem elem[20];\r
+};\r
+\r
#define VPU_SERVICE_SHOW_TIME 0\r
\r
#if VPU_SERVICE_SHOW_TIME\r
\r
#define MHZ (1000*1000)\r
\r
-#if 0\r
-#if defined(CONFIG_ARCH_RK319X)\r
-#define VCODEC_PHYS RK319X_VCODEC_PHYS\r
-#else\r
-#define VCODEC_PHYS (0x10104000)\r
-#endif\r
-#endif\r
-\r
#define REG_NUM_9190_DEC (60)\r
#define REG_NUM_9190_PP (41)\r
#define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
#define REG_NUM_ENC_4831 (164)\r
#define REG_SIZE_ENC_4831 (0x400)\r
\r
-#define REG_NUM_HEVC_DEC (68)\r
+#define REG_NUM_HEVC_DEC (68)\r
\r
#define SIZE_REG(reg) ((reg)*4)\r
\r
.enc_io_size = REG_NUM_ENC_8270 * 4,\r
.dec_offset = REG_SIZE_ENC_8270,\r
.dec_reg_num = REG_NUM_9190_DEC_PP,\r
- .dec_io_size = REG_NUM_9190_DEC_PP * 4,\r
+ .dec_io_size = REG_NUM_9190_DEC_PP * 4,\r
},\r
[1] = {\r
.hw_id = VPU_ID_4831,\r
.enc_io_size = REG_NUM_ENC_4831 * 4,\r
.dec_offset = REG_SIZE_ENC_4831,\r
.dec_reg_num = REG_NUM_9190_DEC_PP,\r
- .dec_io_size = REG_NUM_9190_DEC_PP * 4,\r
+ .dec_io_size = REG_NUM_9190_DEC_PP * 4,\r
},\r
- [2] = {\r
- .hw_id = HEVC_ID,\r
- .hw_addr = 0,\r
- .dec_offset = 0x0,\r
- .dec_reg_num = REG_NUM_HEVC_DEC,\r
- .dec_io_size = REG_NUM_HEVC_DEC * 4,\r
- },\r
+ [2] = {\r
+ .hw_id = HEVC_ID,\r
+ .hw_addr = 0,\r
+ .dec_offset = 0x0,\r
+ .dec_reg_num = REG_NUM_HEVC_DEC,\r
+ .dec_io_size = REG_NUM_HEVC_DEC * 4,\r
+ },\r
+ [3] = {\r
+ .hw_id = VPU_DEC_ID_9190,\r
+ .hw_addr = 0,\r
+ .enc_offset = 0x0,\r
+ .enc_reg_num = 0,\r
+ .enc_io_size = 0,\r
+ .dec_offset = REG_SIZE_ENC_4831,\r
+ .dec_reg_num = REG_NUM_9190_DEC_PP,\r
+ .dec_io_size = REG_NUM_9190_DEC_PP * 4,\r
+ },\r
+\r
};\r
\r
\r
-#define DEC_INTERRUPT_REGISTER 1\r
-#define PP_INTERRUPT_REGISTER 60\r
-#define ENC_INTERRUPT_REGISTER 1\r
+#define DEC_INTERRUPT_REGISTER 1\r
+#define PP_INTERRUPT_REGISTER 60\r
+#define ENC_INTERRUPT_REGISTER 1\r
\r
#define DEC_INTERRUPT_BIT 0x100\r
#define DEC_BUFFER_EMPTY_BIT 0x4000\r
#define PP_INTERRUPT_BIT 0x100\r
#define ENC_INTERRUPT_BIT 0x1\r
\r
-#define HEVC_DEC_INT_RAW_BIT 0x200\r
-#define HEVC_DEC_STR_ERROR_BIT 0x4000\r
-#define HEVC_DEC_BUS_ERROR_BIT 0x2000\r
-#define HEVC_DEC_BUFFER_EMPTY_BIT 0x10000\r
+#define HEVC_DEC_INT_RAW_BIT 0x200\r
+#define HEVC_DEC_STR_ERROR_BIT 0x4000\r
+#define HEVC_DEC_BUS_ERROR_BIT 0x2000\r
+#define HEVC_DEC_BUFFER_EMPTY_BIT 0x10000\r
\r
#define VPU_REG_EN_ENC 14\r
#define VPU_REG_ENC_GATE 2\r
#define VPU_REG_DEC_PP_GATE 61\r
#define VPU_REG_DEC_PP_GATE_BIT (1<<8)\r
\r
+#if defined(CONFIG_VCODEC_MMU)\r
+static u8 addr_tbl_vpu_h264dec[] = {\r
+ 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\r
+ 25, 26, 27, 28, 29, 40, 41\r
+};\r
+\r
+static u8 addr_tbl_vpu_vp8dec[] = {\r
+ 10,12,13, 14, 18, 19, 27, 40\r
+};\r
+\r
+static u8 addr_tbl_vpu_vp6dec[] = {\r
+ 12, 13, 14, 18, 27, 40\r
+};\r
+\r
+static u8 addr_tbl_vpu_vc1dec[] = {\r
+ 12, 13, 14, 15, 16, 17, 27, 41\r
+};\r
+\r
+static u8 addr_tbl_vpu_jpegdec[] = {\r
+ 12, 40, 66, 67\r
+};\r
+\r
+static u8 addr_tbl_vpu_defaultdec[] = {\r
+ 12, 13, 14, 15, 16, 17, 40, 41\r
+};\r
+\r
+static u8 addr_tbl_vpu_enc[] = {\r
+ 5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
+};\r
+\r
+static u8 addr_tbl_hevc_dec[] = {\r
+ 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,\r
+ 21, 22, 23, 24, 42, 43\r
+};\r
+#endif\r
+\r
+enum VPU_DEC_FMT {\r
+ VPU_DEC_FMT_H264,\r
+ VPU_DEC_FMT_MPEG4,\r
+ VPU_DEC_FMT_H263,\r
+ VPU_DEC_FMT_JPEG,\r
+ VPU_DEC_FMT_VC1,\r
+ VPU_DEC_FMT_MPEG2,\r
+ VPU_DEC_FMT_MPEG1,\r
+ VPU_DEC_FMT_VP6,\r
+ VPU_DEC_FMT_RV,\r
+ VPU_DEC_FMT_VP7,\r
+ VPU_DEC_FMT_VP8,\r
+ VPU_DEC_FMT_AVS,\r
+ VPU_DEC_FMT_SVC,\r
+ VPU_DEC_FMT_VC2,\r
+ VPU_DEC_FMT_MVC,\r
+ VPU_DEC_FMT_THEORA,\r
+ VPU_DEC_FMT_RES\r
+};\r
+\r
/**\r
* struct for process session which connect to vpu\r
*\r
struct list_head session_link; /* link to vpu service session */\r
struct list_head status_link; /* link to register set list */\r
unsigned long size;\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ struct list_head mem_region_list;\r
+#endif\r
unsigned long *reg;\r
} vpu_reg;\r
\r
volatile u32 *hwregs;\r
} vpu_device;\r
\r
+enum vcodec_device_id {\r
+ VCODEC_DEVICE_ID_VPU,\r
+ VCODEC_DEVICE_ID_HEVC\r
+};\r
+\r
+struct vcodec_mem_region {\r
+ struct list_head srv_lnk;\r
+ struct list_head reg_lnk;\r
+ struct list_head session_lnk;\r
+ unsigned long iova; /* virtual address for iommu */\r
+ unsigned long len;\r
+ struct ion_handle *hdl;\r
+};\r
+\r
typedef struct vpu_service_info {\r
struct wake_lock wake_lock;\r
struct delayed_work power_off_work;\r
bool bug_dec_addr;\r
atomic_t freq_status;\r
\r
- struct clk *aclk_vcodec;\r
- struct clk *hclk_vcodec;\r
+ struct clk *aclk_vcodec;\r
+ struct clk *hclk_vcodec;\r
+ struct clk *clk_core;\r
+ struct clk *clk_cabac;\r
+ struct clk *pd_video;\r
\r
- int irq_dec;\r
- int irq_enc;\r
+ int irq_dec;\r
+ int irq_enc;\r
\r
- vpu_device enc_dev;\r
- vpu_device dec_dev;\r
+ vpu_device enc_dev;\r
+ vpu_device dec_dev;\r
\r
- struct device *dev;\r
+ struct device *dev;\r
\r
- struct cdev cdev;\r
- dev_t dev_t;\r
- struct class *cls;\r
- struct device *child_dev;\r
+ struct cdev cdev;\r
+ dev_t dev_t;\r
+ struct class *cls;\r
+ struct device *child_dev;\r
+\r
+ struct dentry *debugfs_dir;\r
+ struct dentry *debugfs_file_regs;\r
+\r
+ u32 irq_status;\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ struct ion_client *ion_client;\r
+ struct list_head mem_region_list;\r
+ struct device *mmu_dev;\r
+#endif\r
\r
- struct dentry *debugfs_dir;\r
- struct dentry *debugfs_file_regs;\r
+ enum vcodec_device_id dev_id;\r
\r
- u32 irq_status;\r
+ u32 reserved_mode;\r
\r
- struct delayed_work simulate_work;\r
+ struct delayed_work simulate_work;\r
} vpu_service_info;\r
\r
typedef struct vpu_request\r
{\r
- unsigned long *req;\r
- unsigned long size;\r
+ unsigned long *req;\r
+ unsigned long size;\r
} vpu_request;\r
\r
/// global variable\r
//static struct clk *pd_video;\r
static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
+/* mutex for selecting operation registers of vpu or hevc */\r
+static struct mutex g_mode_mutex;\r
\r
#ifdef CONFIG_DEBUG_FS\r
static int vcodec_debugfs_init(void);\r
\r
#define VPU_POWER_OFF_DELAY 4*HZ /* 4s */\r
#define VPU_TIMEOUT_DELAY 2*HZ /* 2s */\r
+#define VPU_SIMULATE_DELAY msecs_to_jiffies(15)\r
\r
-#define VPU_SIMULATE_DELAY msecs_to_jiffies(5)\r
+#define BIT_VCODEC_SEL_RK3036 (1<<3)\r
+#define BIT_VCODEC_SEL_RK312X (1<<15)\r
+static void vcodec_enter_mode_nolock(enum vcodec_device_id id, u32 *reserved_mode)\r
+{\r
+ if (cpu_is_rk3036() || cpu_is_rk312x()) {\r
+ int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;\r
+ void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);\r
+ if (reserved_mode)\r
+ *reserved_mode = readl_relaxed(addr);\r
+ if (id == VCODEC_DEVICE_ID_HEVC)\r
+ writel_relaxed(readl_relaxed(addr) | (bits) | (bits << 16), addr);\r
+ else\r
+ writel_relaxed((readl_relaxed(addr) & (~bits)) | (bits << 16), addr);\r
+ }\r
+}\r
\r
-static void vpu_get_clk(struct vpu_service_info *pservice)\r
+static void vcodec_exit_mode_nolock(enum vcodec_device_id id, u32 reserved_mode)\r
{\r
- /*pd_video = clk_get(NULL, "pd_video");\r
- if (IS_ERR(pd_video)) {\r
- pr_err("failed on clk_get pd_video\n");\r
- }*/\r
- pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");\r
- if (IS_ERR(pservice->aclk_vcodec)) {\r
- dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
- }\r
- pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");\r
- if (IS_ERR(pservice->hclk_vcodec)) {\r
- dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
+ if (cpu_is_rk3036() || cpu_is_rk312x()) {\r
+ int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;\r
+ void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);\r
+ writel_relaxed(reserved_mode | (bits << 16), addr);\r
}\r
}\r
\r
+static void vcodec_enter_mode(enum vcodec_device_id id)\r
+{\r
+ if (cpu_is_rk3036() || cpu_is_rk312x())\r
+ mutex_lock(&g_mode_mutex);\r
+ vcodec_enter_mode_nolock(id, NULL);\r
+}\r
+\r
+static void vcodec_exit_mode(void)\r
+{\r
+ if (cpu_is_rk3036() || cpu_is_rk312x())\r
+ mutex_unlock(&g_mode_mutex);\r
+}\r
+\r
+static int vpu_get_clk(struct vpu_service_info *pservice)\r
+{\r
+#if VCODEC_CLOCK_ENABLE\r
+ do {\r
+ pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");\r
+ if (IS_ERR(pservice->aclk_vcodec)) {\r
+ dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
+ break;\r
+ }\r
+\r
+ pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");\r
+ if (IS_ERR(pservice->hclk_vcodec)) {\r
+ dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
+ break;\r
+ }\r
+\r
+ if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
+ pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
+ if (IS_ERR(pservice->clk_core)) {\r
+ dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
+ break;\r
+ }\r
+\r
+ if (!cpu_is_rk3036() && !cpu_is_rk312x()) {\r
+ pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
+ if (IS_ERR(pservice->clk_cabac)) {\r
+ dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
+ break;\r
+ }\r
+ } else {\r
+ pservice->clk_cabac = NULL;\r
+ }\r
+\r
+ if (!cpu_is_rk3036() && !cpu_is_rk312x()) {\r
+ pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");\r
+ if (IS_ERR(pservice->pd_video)) {\r
+ dev_err(pservice->dev, "failed on clk_get pd_hevc\n");\r
+ break;\r
+ }\r
+ } else {\r
+ pservice->pd_video = NULL;\r
+ }\r
+ } else {\r
+ if (!cpu_is_rk3036() && !cpu_is_rk312x()) {\r
+ pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
+ if (IS_ERR(pservice->pd_video)) {\r
+ dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
+ break;\r
+ }\r
+ } else {\r
+ pservice->pd_video = NULL;\r
+ }\r
+ }\r
+\r
+ if (cpu_is_rk312x()) {\r
+ pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
+ if (IS_ERR(pservice->pd_video)) {\r
+ dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
+ break;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+ } while (0);\r
+\r
+ return -1;\r
+#else\r
+ return 0;\r
+#endif\r
+}\r
+\r
static void vpu_put_clk(struct vpu_service_info *pservice)\r
{\r
- //clk_put(pd_video);\r
+#if VCODEC_CLOCK_ENABLE\r
+ if (pservice->pd_video) {\r
+ devm_clk_put(pservice->dev, pservice->pd_video);\r
+ }\r
+\r
+ if (pservice->aclk_vcodec) {\r
+ devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
+ }\r
+\r
+ if (pservice->hclk_vcodec) {\r
+ devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
+ }\r
\r
- if (pservice->aclk_vcodec) {\r
- devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
- }\r
+ if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
+ if (pservice->clk_core) {\r
+ devm_clk_put(pservice->dev, pservice->clk_core);\r
+ }\r
\r
- if (pservice->hclk_vcodec) {\r
- devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
- }\r
+ if (pservice->clk_cabac) {\r
+ devm_clk_put(pservice->dev, pservice->clk_cabac);\r
+ }\r
+ }\r
+#endif\r
}\r
\r
static void vpu_reset(struct vpu_service_info *pservice)\r
static void vpu_service_power_off(struct vpu_service_info *pservice)\r
{\r
int total_running;\r
- if (!pservice->enabled) {\r
+ if (!pservice->enabled)\r
return;\r
- }\r
\r
pservice->enabled = false;\r
total_running = atomic_read(&pservice->total_running);\r
vpu_service_dump(pservice);\r
}\r
\r
- printk("vpu: power off...");\r
-#ifdef CONFIG_ARCH_RK29\r
- pmu_set_power_domain(PD_VCODEC, false);\r
-#else\r
- //clk_disable(pd_video);\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ if (pservice->mmu_dev)\r
+ rockchip_iovmm_deactivate(pservice->dev);\r
#endif\r
+\r
+ pr_info("%s: power off...", dev_name(pservice->dev));\r
udelay(10);\r
- //clk_disable(hclk_cpu_vcodec);\r
- //clk_disable(aclk_ddr_vepu);\r
-#if 0\r
- clk_disable_unprepare(pservice->hclk_vcodec);\r
- clk_disable_unprepare(pservice->aclk_vcodec);\r
+#if VCODEC_CLOCK_ENABLE\r
+ if (pservice->pd_video)\r
+ clk_disable_unprepare(pservice->pd_video);\r
+ if (pservice->hclk_vcodec)\r
+ clk_disable_unprepare(pservice->hclk_vcodec);\r
+ if (pservice->aclk_vcodec)\r
+ clk_disable_unprepare(pservice->aclk_vcodec);\r
+ if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
+ if (pservice->clk_core)\r
+ clk_disable_unprepare(pservice->clk_core);\r
+ if (pservice->clk_cabac)\r
+ clk_disable_unprepare(pservice->clk_cabac);\r
+ }\r
#endif\r
wake_unlock(&pservice->wake_lock);\r
- printk("done\n");\r
+ pr_info("done\n");\r
}\r
\r
static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
\r
static void vpu_power_off_work(struct work_struct *work_s)\r
{\r
- struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
- struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
+ struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
+ struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
\r
if (mutex_trylock(&pservice->lock)) {\r
vpu_service_power_off(pservice);\r
return ;\r
\r
pservice->enabled = true;\r
- printk("vpu: power on\n");\r
+ printk("%s: power on\n", dev_name(pservice->dev));\r
+\r
+#if VCODEC_CLOCK_ENABLE\r
+ if (pservice->aclk_vcodec)\r
+ clk_prepare_enable(pservice->aclk_vcodec);\r
+\r
+ if (pservice->hclk_vcodec)\r
+ clk_prepare_enable(pservice->hclk_vcodec);\r
+\r
+ if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
+ if (pservice->clk_core)\r
+ clk_prepare_enable(pservice->clk_core);\r
+ if (pservice->clk_cabac)\r
+ clk_prepare_enable(pservice->clk_cabac);\r
+ }\r
\r
-#if 0\r
- clk_prepare_enable(pservice->aclk_vcodec);\r
- clk_prepare_enable(pservice->hclk_vcodec);\r
+ if (pservice->pd_video)\r
+ clk_prepare_enable(pservice->pd_video);\r
#endif\r
- //clk_prepare_enable(hclk_cpu_vcodec);\r
+\r
#if defined(CONFIG_ARCH_RK319X)\r
- /// select aclk_vepu as vcodec clock source. \r
- #define BIT_VCODEC_SEL (1<<7)\r
- writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
-#endif\r
- udelay(10);\r
-#ifdef CONFIG_ARCH_RK29\r
- pmu_set_power_domain(PD_VCODEC, true);\r
-#else\r
- //clk_enable(pd_video);\r
+ /// select aclk_vepu as vcodec clock source. \r
+#define BIT_VCODEC_SEL (1<<7)\r
+ writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) |\r
+ (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16),\r
+ RK319X_GRF_BASE + GRF_SOC_CON1);\r
#endif\r
+#define BIT_VCODEC_CLK_SEL (1<<10)\r
+ if (cpu_is_rk312x())\r
+ writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |\r
+ BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),\r
+ RK_GRF_VIRT + RK312X_GRF_SOC_CON1);\r
+\r
+\r
udelay(10);\r
- //clk_enable(aclk_ddr_vepu);\r
wake_lock(&pservice->wake_lock);\r
+\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ if (pservice->mmu_dev)\r
+ rockchip_iovmm_activate(pservice->dev);\r
+#endif \r
}\r
\r
static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
return (type > 0);\r
}\r
\r
+static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)\r
+{\r
+ enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);\r
+ return type;\r
+}\r
+\r
+static inline int reg_probe_width(vpu_reg *reg)\r
+{\r
+ int width_in_mb = reg->reg[4] >> 23;\r
+ return width_in_mb * 16;\r
+}\r
+\r
+#if defined(CONFIG_VCODEC_MMU)\r
+static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl,\r
+ int size, vpu_reg *reg,\r
+ struct extra_info_for_iommu *ext_inf)\r
+{\r
+ int i;\r
+ int usr_fd = 0;\r
+ int offset = 0;\r
+\r
+ if (tbl == NULL || size <= 0) {\r
+ dev_err(pservice->dev, "input arguments invalidate\n");\r
+ return -1;\r
+ }\r
+\r
+ vpu_service_power_on(pservice);\r
+\r
+ for (i = 0; i < size; i++) {\r
+ usr_fd = reg->reg[tbl[i]] & 0x3FF;\r
+\r
+ if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID &&\r
+ (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))\r
+ /* special for vpu dec num 41 regitster */\r
+ offset = reg->reg[tbl[i]] >> 10 << 4;\r
+ else\r
+ offset = reg->reg[tbl[i]] >> 10;\r
+\r
+ if (usr_fd != 0) {\r
+ struct ion_handle *hdl;\r
+ int ret;\r
+ struct vcodec_mem_region *mem_region;\r
+\r
+ hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
+ if (IS_ERR(hdl)) {\r
+ dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);\r
+ return PTR_ERR(hdl);\r
+ }\r
+\r
+ mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
+\r
+ if (mem_region == NULL) {\r
+ dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
+ ion_free(pservice->ion_client, hdl);\r
+ return -1;\r
+ }\r
+\r
+ mem_region->hdl = hdl;\r
+\r
+ vcodec_enter_mode(pservice->dev_id);\r
+ ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);\r
+ vcodec_exit_mode();\r
+ if (ret < 0) {\r
+ dev_err(pservice->dev, "ion map iommu failed\n");\r
+ kfree(mem_region);\r
+ ion_free(pservice->ion_client, hdl);\r
+ return ret;\r
+ }\r
+ reg->reg[tbl[i]] = mem_region->iova + offset;\r
+ INIT_LIST_HEAD(&mem_region->reg_lnk);\r
+ list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);\r
+ }\r
+ }\r
+\r
+ if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {\r
+ for (i=0; i<ext_inf->cnt; i++) {\r
+ pr_info("reg[%d] + offset %d\n", ext_inf->elem[i].index, ext_inf->elem[i].offset);\r
+ reg->reg[ext_inf->elem[i].index] += ext_inf->elem[i].offset;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+static int vcodec_reg_address_translate(struct vpu_service_info *pservice,\r
+ vpu_reg *reg,\r
+ struct extra_info_for_iommu *ext_inf)\r
+{\r
+ VPU_HW_ID hw_id;\r
+ u8 *tbl;\r
+ int size = 0;\r
+\r
+ hw_id = pservice->hw_info->hw_id;\r
+\r
+ if (hw_id == HEVC_ID) {\r
+ tbl = addr_tbl_hevc_dec;\r
+ size = sizeof(addr_tbl_hevc_dec);\r
+ } else {\r
+ if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
+ switch (reg_check_fmt(reg)) {\r
+ case VPU_DEC_FMT_H264:\r
+ {\r
+ tbl = addr_tbl_vpu_h264dec;\r
+ size = sizeof(addr_tbl_vpu_h264dec);\r
+ break;\r
+ }\r
+ case VPU_DEC_FMT_VP8:\r
+ case VPU_DEC_FMT_VP7:\r
+ {\r
+ tbl = addr_tbl_vpu_vp8dec;\r
+ size = sizeof(addr_tbl_vpu_vp8dec);\r
+ break;\r
+ }\r
+\r
+ case VPU_DEC_FMT_VP6:\r
+ {\r
+ tbl = addr_tbl_vpu_vp6dec;\r
+ size = sizeof(addr_tbl_vpu_vp6dec);\r
+ break;\r
+ }\r
+ case VPU_DEC_FMT_VC1:\r
+ {\r
+ tbl = addr_tbl_vpu_vc1dec;\r
+ size = sizeof(addr_tbl_vpu_vc1dec);\r
+ break;\r
+ }\r
+\r
+ case VPU_DEC_FMT_JPEG:\r
+ {\r
+ tbl = addr_tbl_vpu_jpegdec;\r
+ size = sizeof(addr_tbl_vpu_jpegdec);\r
+ break;\r
+ }\r
+ default:\r
+ tbl = addr_tbl_vpu_defaultdec;\r
+ size = sizeof(addr_tbl_vpu_defaultdec);\r
+ break;\r
+ }\r
+ } else if (reg->type == VPU_ENC) {\r
+ tbl = addr_tbl_vpu_enc;\r
+ size = sizeof(addr_tbl_vpu_enc);\r
+ }\r
+ }\r
+\r
+ if (size != 0) {\r
+ return vcodec_bufid_to_iova(pservice, tbl, size, reg, ext_inf);\r
+ } else {\r
+ return -1;\r
+ }\r
+}\r
+#endif\r
+\r
static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
{\r
+ int extra_size = 0;\r
+ struct extra_info_for_iommu extra_info;\r
vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
if (NULL == reg) {\r
pr_err("error: kmalloc fail in reg_init\n");\r
}\r
\r
if (size > pservice->reg_size) {\r
- printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
+ /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
+ size = pservice->reg_size;*/\r
+ extra_size = size - pservice->reg_size;\r
size = pservice->reg_size;\r
}\r
reg->session = session;\r
INIT_LIST_HEAD(®->session_link);\r
INIT_LIST_HEAD(®->status_link);\r
\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ if (pservice->mmu_dev)\r
+ INIT_LIST_HEAD(®->mem_region_list);\r
+#endif\r
+\r
if (copy_from_user(®->reg[0], (void __user *)src, size)) {\r
pr_err("error: copy_from_user failed in reg_init\n");\r
kfree(reg);\r
return NULL;\r
}\r
\r
+ if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {\r
+ pr_err("error: copy_from_user failed in reg_init\n");\r
+ kfree(reg);\r
+ return NULL;\r
+ }\r
+\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ if (pservice->mmu_dev && 0 > vcodec_reg_address_translate(pservice, reg, &extra_info)) {\r
+ pr_err("error: translate reg address failed\n");\r
+ kfree(reg);\r
+ return NULL;\r
+ }\r
+#endif\r
+\r
mutex_lock(&pservice->lock);\r
list_add_tail(®->status_link, &pservice->waiting);\r
list_add_tail(®->session_link, &session->waiting);\r
if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
if (reg_check_rmvb_wmv(reg)) {\r
reg->freq = VPU_FREQ_200M;\r
+ } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {\r
+ if (reg_probe_width(reg) > 3200) {\r
+ // raise frequency for 4k avc.\r
+ reg->freq = VPU_FREQ_500M;\r
+ }\r
} else {\r
if (reg_check_interlace(reg)) {\r
reg->freq = VPU_FREQ_400M;\r
\r
static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
{\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ struct vcodec_mem_region *mem_region = NULL, *n;\r
+#endif\r
+\r
list_del_init(®->session_link);\r
list_del_init(®->status_link);\r
- if (reg == pservice->reg_codec) pservice->reg_codec = NULL;\r
- if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;\r
+ if (reg == pservice->reg_codec)\r
+ pservice->reg_codec = NULL;\r
+ if (reg == pservice->reg_pproc)\r
+ pservice->reg_pproc = NULL;\r
+\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ // release memory region attach to this registers table.\r
+ if (pservice->mmu_dev) {\r
+ list_for_each_entry_safe(mem_region, n, ®->mem_region_list, reg_lnk) {\r
+ /* do not unmap iommu manually,\r
+ unmap will proccess when memory release */\r
+ /*vcodec_enter_mode(pservice->dev_id);\r
+ ion_unmap_iommu(pservice->dev,\r
+ pservice->ion_client,\r
+ mem_region->hdl);\r
+ vcodec_exit_mode();*/\r
+ ion_free(pservice->ion_client, mem_region->hdl);\r
+ list_del_init(&mem_region->reg_lnk);\r
+ kfree(mem_region);\r
+ }\r
+ }\r
+#endif\r
+\r
kfree(reg);\r
}\r
\r
{\r
int i;\r
u32 *dst = (u32 *)®->reg[0];\r
+\r
for (i = 0; i < count; i++)\r
*dst++ = *src++;\r
}\r
\r
static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
{\r
- int irq_reg = -1;\r
+ int irq_reg = -1;\r
list_del_init(®->status_link);\r
list_add_tail(®->status_link, &pservice->done);\r
\r
list_del_init(®->session_link);\r
list_add_tail(®->session_link, ®->session->done);\r
\r
+ vcodec_enter_mode(pservice->dev_id);\r
switch (reg->type) {\r
case VPU_ENC : {\r
pservice->reg_codec = NULL;\r
reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
- irq_reg = ENC_INTERRUPT_REGISTER;\r
+ irq_reg = ENC_INTERRUPT_REGISTER;\r
break;\r
}\r
case VPU_DEC : {\r
+ int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
pservice->reg_codec = NULL;\r
- reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC);\r
- irq_reg = DEC_INTERRUPT_REGISTER;\r
+ reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);\r
+ irq_reg = DEC_INTERRUPT_REGISTER;\r
break;\r
}\r
case VPU_PP : {\r
break;\r
}\r
}\r
+ vcodec_exit_mode();\r
\r
- if (irq_reg != -1) {\r
- reg->reg[irq_reg] = pservice->irq_status;\r
- }\r
+ if (irq_reg != -1) {\r
+ reg->reg[irq_reg] = pservice->irq_status;\r
+ }\r
\r
atomic_sub(1, ®->session->task_running);\r
atomic_sub(1, &pservice->total_running);\r
clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
//printk("default: 400M\n");\r
} break;\r
+ case VPU_FREQ_500M : {\r
+ clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
+ } break;\r
+ case VPU_FREQ_600M : {\r
+ clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
+ } break;\r
default : {\r
if (soc_is_rk2928g()) {\r
clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
if (pservice->auto_freq) {\r
vpu_service_set_freq(pservice, reg);\r
}\r
+\r
+ vcodec_enter_mode(pservice->dev_id);\r
+\r
switch (reg->type) {\r
case VPU_ENC : {\r
int enc_count = pservice->hw_info->enc_reg_num;\r
u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
-#if 0\r
- if (pservice->bug_dec_addr) {\r
-#if !defined(CONFIG_ARCH_RK319X)\r
- cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
-#endif\r
- cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
- cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
-#if !defined(CONFIG_ARCH_RK319X)\r
- cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
-#endif\r
- }\r
-#endif\r
+\r
pservice->reg_codec = reg;\r
\r
dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
} break;\r
case VPU_DEC : {\r
u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
+\r
pservice->reg_codec = reg;\r
\r
- for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
- dst[i] = src[i];\r
+ if (pservice->hw_info->hw_id != HEVC_ID) {\r
+ for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
+ dst[i] = src[i];\r
+ } else {\r
+ for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
+ dst[i] = src[i];\r
+ }\r
+ }\r
\r
dsb();\r
\r
- dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
- dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
+ if (pservice->hw_info->hw_id != HEVC_ID) {\r
+ dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
+ dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
+ } else {\r
+ dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
+ }\r
+\r
+ dsb();\r
+ dmb();\r
\r
#if VPU_SERVICE_SHOW_TIME\r
do_gettimeofday(&dec_start);\r
}\r
}\r
\r
+ vcodec_exit_mode();\r
+\r
#if HEVC_SIM_ENABLE\r
- if (pservice->hw_info->hw_id == HEVC_ID) {\r
- simulate_start(pservice);\r
- }\r
+ if (pservice->hw_info->hw_id == HEVC_ID) {\r
+ simulate_start(pservice);\r
+ }\r
#endif\r
}\r
\r
break;\r
}\r
case VPU_DEC : {\r
- if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC)))\r
+ int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
+ if (copy_to_user(dst, ®->reg[0], SIZE_REG(reg_len)))\r
ret = -EFAULT;\r
break;\r
}\r
mutex_unlock(&pservice->lock);\r
break;\r
}\r
+ case VPU_IOC_PROBE_IOMMU_STATUS: {\r
+ int iommu_enable = 0;\r
+\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ iommu_enable = pservice->mmu_dev ? 1 : 0;\r
+#endif\r
+\r
+ if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {\r
+ pr_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");\r
+ return -EFAULT;\r
+ }\r
+ break;\r
+ }\r
default : {\r
pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
break;\r
volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
u32 enc_id = *tmp;\r
\r
-#if 0\r
- /// temporary, hevc driver test.\r
- if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
- p->hw_info = &vpu_hw_set[2];\r
- return 0;\r
- }\r
+#if HEVC_SIM_ENABLE\r
+ /// temporary, hevc driver test.\r
+ if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
+ p->hw_info = &vpu_hw_set[2];\r
+ return 0;\r
+ }\r
#endif\r
-\r
enc_id = (enc_id >> 16) & 0xFFFF;\r
pr_info("checking hw id %x\n", enc_id);\r
- p->hw_info = NULL;\r
+ p->hw_info = NULL;\r
for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
if (enc_id == vpu_hw_set[i].hw_id) {\r
p->hw_info = &vpu_hw_set[i];\r
\r
static int vpu_service_open(struct inode *inode, struct file *filp)\r
{\r
- struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
+ struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
if (NULL == session) {\r
pr_err("error: unable to allocate memory for vpu_session.");\r
\r
static int vpu_service_release(struct inode *inode, struct file *filp)\r
{\r
- struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
+ struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
int task_running;\r
vpu_session *session = (vpu_session *)filp->private_data;\r
if (NULL == session)\r
filp->private_data = NULL;\r
mutex_unlock(&pservice->lock);\r
\r
- pr_debug("dev closed\n");\r
+ pr_debug("dev closed\n");\r
return 0;\r
}\r
\r
#if HEVC_SIM_ENABLE\r
static void simulate_work(struct work_struct *work_s)\r
{\r
- struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
- struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
- vpu_device *dev = &pservice->dec_dev;\r
-\r
- if (!list_empty(&pservice->running)) {\r
- atomic_add(1, &dev->irq_count_codec);\r
- vdpu_isr(0, (void*)pservice);\r
- } else {\r
- //simulate_start(pservice);\r
- pr_err("empty running queue\n");\r
- }\r
+ struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
+ struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
+ vpu_device *dev = &pservice->dec_dev;\r
+\r
+ if (!list_empty(&pservice->running)) {\r
+ atomic_add(1, &dev->irq_count_codec);\r
+ vdpu_isr(0, (void*)pservice);\r
+ } else {\r
+ //simulate_start(pservice);\r
+ pr_err("empty running queue\n");\r
+ }\r
}\r
\r
static void simulate_init(struct vpu_service_info *pservice)\r
{\r
- INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
+ INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
}\r
\r
static void simulate_start(struct vpu_service_info *pservice)\r
{\r
- cancel_delayed_work_sync(&pservice->power_off_work);\r
- queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
+ cancel_delayed_work_sync(&pservice->power_off_work);\r
+ queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
}\r
#endif\r
\r
+#ifdef CONFIG_VCODEC_MMU\r
+static struct device *rockchip_get_sysmmu_device_by_compatible(const char *compt)\r
+{\r
+ struct device_node *dn = NULL;\r
+ struct platform_device *pd = NULL;\r
+ struct device *ret = NULL ;\r
+\r
+ dn = of_find_compatible_node(NULL,NULL,compt);\r
+ if(!dn) {\r
+ printk("can't find device node %s \r\n",compt);\r
+ return NULL;\r
+ }\r
+ \r
+ pd = of_find_device_by_node(dn);\r
+ if(!pd) { \r
+ printk("can't find platform device in device node %s \r\n",compt);\r
+ return NULL;\r
+ }\r
+ ret = &pd->dev;\r
+ \r
+ return ret;\r
+\r
+}\r
+#ifdef CONFIG_IOMMU_API\r
+static inline void platform_set_sysmmu(struct device *iommu, struct device *dev)\r
+{\r
+ dev->archdata.iommu = iommu;\r
+}\r
+#else\r
+static inline void platform_set_sysmmu(struct device *iommu, struct device *dev)\r
+{\r
+}\r
+#endif\r
+#endif\r
+\r
#if HEVC_TEST_ENABLE\r
static int hevc_test_case0(vpu_service_info *pservice);\r
#endif\r
+#if defined(CONFIG_ION_ROCKCHIP)\r
+extern struct ion_client *rockchip_ion_client_create(const char * name);\r
+#endif\r
static int vcodec_probe(struct platform_device *pdev)\r
{\r
- int ret = 0;\r
- struct resource *res = NULL;\r
- struct device *dev = &pdev->dev;\r
- void __iomem *regs = NULL;\r
- struct device_node *np = pdev->dev.of_node;\r
- struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
- char *prop = (char*)dev_name(dev);\r
-\r
- pr_info("probe device %s\n", dev_name(dev));\r
-\r
- of_property_read_string(np, "name", (const char**)&prop);\r
- dev_set_name(dev, prop);\r
-\r
- wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
- INIT_LIST_HEAD(&pservice->waiting);\r
- INIT_LIST_HEAD(&pservice->running);\r
- INIT_LIST_HEAD(&pservice->done);\r
- INIT_LIST_HEAD(&pservice->session);\r
- mutex_init(&pservice->lock);\r
- pservice->reg_codec = NULL;\r
- pservice->reg_pproc = NULL;\r
- atomic_set(&pservice->total_running, 0);\r
- pservice->enabled = false;\r
-\r
- pservice->dev = dev;\r
+ int ret = 0;\r
+ struct resource *res = NULL;\r
+ struct device *dev = &pdev->dev;\r
+ void __iomem *regs = NULL;\r
+ struct device_node *np = pdev->dev.of_node;\r
+ struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
+ char *prop = (char*)dev_name(dev);\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ u32 iommu_en = 0;\r
+ char mmu_dev_dts_name[40];\r
+ of_property_read_u32(np, "iommu_enabled", &iommu_en);\r
+#endif\r
\r
- vpu_get_clk(pservice);\r
-\r
- INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
+ pr_info("probe device %s\n", dev_name(dev));\r
\r
- vpu_service_power_on(pservice);\r
+ of_property_read_string(np, "name", (const char**)&prop);\r
+ dev_set_name(dev, prop);\r
\r
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
+ if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
+ pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
+ } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
+ pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
+ } else {\r
+ dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
+ return -1;\r
+ }\r
\r
- regs = devm_ioremap_resource(pservice->dev, res);\r
- if (IS_ERR(regs)) {\r
- ret = PTR_ERR(regs);\r
- goto err;\r
- }\r
+ mutex_init(&g_mode_mutex);\r
+ vcodec_enter_mode(pservice->dev_id);\r
+\r
+ wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
+ INIT_LIST_HEAD(&pservice->waiting);\r
+ INIT_LIST_HEAD(&pservice->running);\r
+ INIT_LIST_HEAD(&pservice->done);\r
+ INIT_LIST_HEAD(&pservice->session);\r
+ mutex_init(&pservice->lock);\r
+ pservice->reg_codec = NULL;\r
+ pservice->reg_pproc = NULL;\r
+ atomic_set(&pservice->total_running, 0);\r
+ pservice->enabled = false;\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ pservice->mmu_dev = NULL;\r
+#endif\r
+ pservice->dev = dev;\r
\r
- ret = vpu_service_check_hw(pservice, res->start);\r
- if (ret < 0) {\r
- pr_err("error: hw info check faild\n");\r
- goto err;\r
- }\r
+ if (0 > vpu_get_clk(pservice))\r
+ goto err;\r
\r
- /// define regs address.\r
- pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
- pservice->dec_dev.iosize = pservice->hw_info->dec_io_size;\r
+ INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
\r
- pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
+ vpu_service_power_on(pservice);\r
\r
- pservice->reg_size = pservice->dec_dev.iosize;\r
+ mdelay(1);\r
\r
- if (pservice->hw_info->hw_id != HEVC_ID) {\r
- pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
- pservice->enc_dev.iosize = pservice->hw_info->enc_io_size;\r
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
\r
- pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
+ res->flags &= ~IORESOURCE_CACHEABLE;\r
\r
- pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
+ regs = devm_ioremap_resource(pservice->dev, res);\r
+ if (IS_ERR(regs)) {\r
+ ret = PTR_ERR(regs);\r
+ goto err;\r
+ }\r
\r
- pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
- if (pservice->irq_enc < 0) {\r
- dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
- ret = -ENXIO;\r
- goto err;\r
- }\r
+ {\r
+ u32 offset = res->start;\r
+ if (cpu_is_rk3036()) {\r
+ if (pservice->dev_id == VCODEC_DEVICE_ID_VPU)\r
+ offset += 0x400;\r
+ }\r
+ ret = vpu_service_check_hw(pservice, offset);\r
+ if (ret < 0) {\r
+ pr_err("error: hw info check faild\n");\r
+ goto err;\r
+ }\r
+ }\r
\r
- ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
- if (ret) {\r
- dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
- goto err;\r
- }\r
- }\r
+ /// define regs address.\r
+ pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
+ pservice->dec_dev.iosize = pservice->hw_info->dec_io_size;\r
\r
- pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
- if (pservice->irq_dec < 0) {\r
- dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
- ret = -ENXIO;\r
- goto err;\r
- }\r
+ pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
\r
- /* get the IRQ line */\r
- ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
- if (ret) {\r
- dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
- goto err;\r
- }\r
+ pservice->reg_size = pservice->dec_dev.iosize;\r
\r
- atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
- atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
- atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
- atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
+ if (pservice->hw_info->hw_id != HEVC_ID && !cpu_is_rk3036()) {\r
+ pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
+ pservice->enc_dev.iosize = pservice->hw_info->enc_io_size;\r
\r
- /// create device\r
- ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
- if (ret) {\r
- dev_err(dev, "alloc dev_t failed\n");\r
- goto err;\r
- }\r
+ pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
\r
- cdev_init(&pservice->cdev, &vpu_service_fops);\r
+ pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
\r
- pservice->cdev.owner = THIS_MODULE;\r
- pservice->cdev.ops = &vpu_service_fops;\r
+ pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
+ if (pservice->irq_enc < 0) {\r
+ dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
+ ret = -ENXIO;\r
+ goto err;\r
+ }\r
\r
- ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
+ ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
+ if (ret) {\r
+ dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
+ goto err;\r
+ }\r
+ }\r
\r
- if (ret) {\r
- dev_err(dev, "add dev_t failed\n");\r
- goto err;\r
- }\r
+ pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
+ if (pservice->irq_dec < 0) {\r
+ dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
+ ret = -ENXIO;\r
+ goto err;\r
+ }\r
\r
- pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
+ /* get the IRQ line */\r
+ ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
+ if (ret) {\r
+ dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
+ goto err;\r
+ }\r
\r
- if (IS_ERR(pservice->cls)) {\r
- ret = PTR_ERR(pservice->cls);\r
- dev_err(dev, "class_create err:%d\n", ret);\r
- goto err;\r
- }\r
+ atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
+ atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
+ atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
+ atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
\r
- pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
+ /// create device\r
+ ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
+ if (ret) {\r
+ dev_err(dev, "alloc dev_t failed\n");\r
+ goto err;\r
+ }\r
+\r
+ cdev_init(&pservice->cdev, &vpu_service_fops);\r
+\r
+ pservice->cdev.owner = THIS_MODULE;\r
+ pservice->cdev.ops = &vpu_service_fops;\r
\r
- platform_set_drvdata(pdev, pservice);\r
+ ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
+\r
+ if (ret) {\r
+ dev_err(dev, "add dev_t failed\n");\r
+ goto err;\r
+ }\r
+\r
+ pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
+\r
+ if (IS_ERR(pservice->cls)) {\r
+ ret = PTR_ERR(pservice->cls);\r
+ dev_err(dev, "class_create err:%d\n", ret);\r
+ goto err;\r
+ }\r
+\r
+ pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
+\r
+ platform_set_drvdata(pdev, pservice);\r
+\r
+ get_hw_info(pservice);\r
\r
- if (pservice->hw_info->hw_id != HEVC_ID) {\r
- get_hw_info(pservice);\r
- }\r
\r
#ifdef CONFIG_DEBUG_FS\r
- pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
- \r
- if (pservice->debugfs_dir == NULL) {\r
- pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
- }\r
-\r
- pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
- pservice->debugfs_dir, pservice,\r
- &debug_vcodec_fops);\r
+ pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
+ if (pservice->debugfs_dir == NULL)\r
+ pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
+\r
+ pservice->debugfs_file_regs =\r
+ debugfs_create_file("regs", 0664,\r
+ pservice->debugfs_dir, pservice,\r
+ &debug_vcodec_fops);\r
+#endif\r
+\r
+#if defined(CONFIG_VCODEC_MMU)\r
+ if (iommu_en) {\r
+ pservice->ion_client = rockchip_ion_client_create("vpu");\r
+ if (IS_ERR(pservice->ion_client)) {\r
+ dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
+ return PTR_ERR(pservice->ion_client);\r
+ } else {\r
+ dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
+ }\r
+\r
+ if (pservice->hw_info->hw_id == HEVC_ID)\r
+ sprintf(mmu_dev_dts_name, HEVC_IOMMU_COMPATIBLE_NAME);\r
+ else\r
+ sprintf(mmu_dev_dts_name, VPU_IOMMU_COMPATIBLE_NAME);\r
+\r
+ pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
+\r
+ if (pservice->mmu_dev) {\r
+ platform_set_sysmmu(pservice->mmu_dev, pservice->dev);\r
+ rockchip_iovmm_activate(pservice->dev);\r
+ }\r
+ }\r
#endif\r
\r
- vpu_service_power_off(pservice);\r
- pr_info("init success\n");\r
+ vpu_service_power_off(pservice);\r
+ vcodec_exit_mode();\r
+\r
+ pr_info("init success\n");\r
\r
#if HEVC_SIM_ENABLE\r
- if (pservice->hw_info->hw_id == HEVC_ID) {\r
- simulate_init(pservice);\r
- }\r
+ if (pservice->hw_info->hw_id == HEVC_ID)\r
+ simulate_init(pservice);\r
#endif\r
\r
#if HEVC_TEST_ENABLE\r
- hevc_test_case0(pservice);\r
+ hevc_test_case0(pservice);\r
#endif\r
\r
- return 0;\r
+ return 0;\r
\r
err:\r
- pr_info("init failed\n");\r
- vpu_service_power_off(pservice);\r
- vpu_put_clk(pservice);\r
- wake_lock_destroy(&pservice->wake_lock);\r
-\r
- if (res) {\r
- if (regs) {\r
- devm_ioremap_release(&pdev->dev, res);\r
- }\r
- devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
- }\r
-\r
- if (pservice->irq_enc > 0) {\r
- free_irq(pservice->irq_enc, (void *)pservice);\r
- }\r
-\r
- if (pservice->irq_dec > 0) {\r
- free_irq(pservice->irq_dec, (void *)pservice);\r
- }\r
-\r
- if (pservice->child_dev) {\r
- device_destroy(pservice->cls, pservice->dev_t);\r
- cdev_del(&pservice->cdev);\r
- unregister_chrdev_region(pservice->dev_t, 1);\r
- }\r
-\r
- if (pservice->cls) {\r
- class_destroy(pservice->cls);\r
- }\r
-\r
- return ret;\r
+ pr_info("init failed\n");\r
+ vpu_service_power_off(pservice);\r
+ vpu_put_clk(pservice);\r
+ wake_lock_destroy(&pservice->wake_lock);\r
+\r
+ if (res)\r
+ devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
+ if (pservice->irq_enc > 0)\r
+ free_irq(pservice->irq_enc, (void *)pservice);\r
+ if (pservice->irq_dec > 0)\r
+ free_irq(pservice->irq_dec, (void *)pservice);\r
+\r
+ if (pservice->child_dev) {\r
+ device_destroy(pservice->cls, pservice->dev_t);\r
+ cdev_del(&pservice->cdev);\r
+ unregister_chrdev_region(pservice->dev_t, 1);\r
+ }\r
+\r
+ if (pservice->cls)\r
+ class_destroy(pservice->cls);\r
+\r
+ return ret;\r
}\r
\r
static int vcodec_remove(struct platform_device *pdev)\r
{\r
- struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
- struct resource *res;\r
-\r
- device_destroy(pservice->cls, pservice->dev_t);\r
- class_destroy(pservice->cls);\r
- cdev_del(&pservice->cdev);\r
- unregister_chrdev_region(pservice->dev_t, 1);\r
-\r
- free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
- free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
- devm_ioremap_release(&pdev->dev, res);\r
- devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
- vpu_put_clk(pservice);\r
- wake_lock_destroy(&pservice->wake_lock);\r
- \r
-#ifdef CONFIG_DEBUG_FS\r
- if (pservice->debugfs_file_regs) {\r
- debugfs_remove(pservice->debugfs_file_regs);\r
- }\r
+ struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
+ struct resource *res;\r
+\r
+ device_destroy(pservice->cls, pservice->dev_t);\r
+ class_destroy(pservice->cls);\r
+ cdev_del(&pservice->cdev);\r
+ unregister_chrdev_region(pservice->dev_t, 1);\r
\r
- if (pservice->debugfs_dir) {\r
- debugfs_remove(pservice->debugfs_dir);\r
- }\r
+ free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
+ free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
+ devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
+ vpu_put_clk(pservice);\r
+ wake_lock_destroy(&pservice->wake_lock);\r
+\r
+#ifdef CONFIG_DEBUG_FS\r
+ debugfs_remove(pservice->debugfs_file_regs);\r
+ debugfs_remove(pservice->debugfs_dir);\r
#endif\r
\r
- return 0;\r
+ return 0;\r
}\r
\r
#if defined(CONFIG_OF)\r
static const struct of_device_id vcodec_service_dt_ids[] = {\r
- //{.compatible = "vpu_service",},\r
+ {.compatible = "vpu_service",},\r
{.compatible = "rockchip,hevc_service",},\r
- {},\r
+ {},\r
};\r
#endif\r
\r
static struct platform_driver vcodec_driver = {\r
- .probe = vcodec_probe,\r
- .remove = vcodec_remove,\r
- .driver = {\r
- .name = "vcodec",\r
- .owner = THIS_MODULE,\r
+ .probe = vcodec_probe,\r
+ .remove = vcodec_remove,\r
+ .driver = {\r
+ .name = "vcodec",\r
+ .owner = THIS_MODULE,\r
#if defined(CONFIG_OF)\r
- .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
+ .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
#endif\r
},\r
};\r
{\r
VPUHwDecConfig_t *dec = &pservice->dec_config;\r
VPUHwEncConfig_t *enc = &pservice->enc_config;\r
- u32 configReg = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
- u32 asicID = pservice->dec_dev.hwregs[0];\r
-\r
- dec->h264Support = (configReg >> DWL_H264_E) & 0x3U;\r
- dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;\r
- if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
- dec->jpegSupport = JPEG_PROGRESSIVE;\r
- dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;\r
- dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;\r
- dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;\r
- dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
- dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
- dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;\r
-#if !defined(CONFIG_ARCH_RK319X)\r
- /// invalidate max decode picture width value in rk319x vpu\r
- dec->maxDecPicWidth = configReg & 0x07FFU;\r
-#else\r
- dec->maxDecPicWidth = 3840;\r
-#endif\r
-\r
- /* 2nd Config register */\r
- configReg = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
- if (dec->refBufSupport) {\r
- if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
- dec->refBufSupport |= 2;\r
- if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
- dec->refBufSupport |= 4;\r
- }\r
- dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
- dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;\r
- dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;\r
- dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;\r
-\r
- /* JPEG xtensions */\r
- if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
- dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
- } else {\r
- dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
- }\r
-\r
- if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
- dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
- } else {\r
- dec->rvSupport = RV_NOT_SUPPORTED;\r
- }\r
\r
- dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
+ if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {\r
+ u32 configReg = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
+ u32 asicID = pservice->dec_dev.hwregs[0];\r
+\r
+ dec->h264Support = (configReg >> DWL_H264_E) & 0x3U;\r
+ dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;\r
+ if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
+ dec->jpegSupport = JPEG_PROGRESSIVE;\r
+ dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;\r
+ dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;\r
+ dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;\r
+ dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
+ dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
+ dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;\r
+\r
+ if (soc_is_rk3190() || soc_is_rk3288())\r
+ dec->maxDecPicWidth = 4096;\r
+ else if (cpu_is_rk3036() || cpu_is_rk312x())\r
+ dec->maxDecPicWidth = 1920;\r
+ else\r
+ dec->maxDecPicWidth = configReg & 0x07FFU;\r
+\r
+ /* 2nd Config register */\r
+ configReg = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
+ if (dec->refBufSupport) {\r
+ if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
+ dec->refBufSupport |= 2;\r
+ if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
+ dec->refBufSupport |= 4;\r
+ }\r
+ dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
+ dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;\r
+ dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;\r
+ dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;\r
+\r
+ /* JPEG xtensions */\r
+ if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))\r
+ dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
+ else\r
+ dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
+\r
+ if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )\r
+ dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
+ else\r
+ dec->rvSupport = RV_NOT_SUPPORTED;\r
+ dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
+\r
+ if (dec->refBufSupport && (asicID >> 16) == 0x6731U )\r
+ dec->refBufSupport |= 8; /* enable HW support for offset */\r
+\r
+ /// invalidate fuse register value in rk319x vpu and following.\r
+ if (!soc_is_rk3190() && !soc_is_rk3288() && !cpu_is_rk3036() && !cpu_is_rk312x()) {\r
+ VPUHwFuseStatus_t hwFuseSts;\r
+ /* Decoder fuse configuration */\r
+ u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
+\r
+ hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
+ hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
+ hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
+ hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
+ hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
+ hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
+ hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
+ hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
+ hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
+ hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
+ hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
+ hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
+ hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
+ hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
+\r
+ /* check max. decoder output width */\r
+\r
+ if (fuseReg & 0x8000U)\r
+ hwFuseSts.maxDecPicWidthFuse = 1920;\r
+ else if (fuseReg & 0x4000U)\r
+ hwFuseSts.maxDecPicWidthFuse = 1280;\r
+ else if (fuseReg & 0x2000U)\r
+ hwFuseSts.maxDecPicWidthFuse = 720;\r
+ else if (fuseReg & 0x1000U)\r
+ hwFuseSts.maxDecPicWidthFuse = 352;\r
+ else /* remove warning */\r
+ hwFuseSts.maxDecPicWidthFuse = 352;\r
+\r
+ hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
+\r
+ /* Pp configuration */\r
+ configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
+\r
+ if ((configReg >> DWL_PP_E) & 0x01U) {\r
+ dec->ppSupport = 1;\r
+ dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
+ /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
+ dec->ppConfig = configReg;\r
+ } else {\r
+ dec->ppSupport = 0;\r
+ dec->maxPpOutPicWidth = 0;\r
+ dec->ppConfig = 0;\r
+ }\r
\r
- if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
- dec->refBufSupport |= 8; /* enable HW support for offset */\r
- }\r
+ /* check the HW versio */\r
+ if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
+ /* Pp configuration */\r
+ configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
+ if ((configReg >> DWL_PP_E) & 0x01U) {\r
+ /* Pp fuse configuration */\r
+ u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
+\r
+ if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
+ hwFuseSts.ppSupportFuse = 1;\r
+ /* check max. pp output width */\r
+ if (fuseRegPp & 0x8000U)\r
+ hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
+ else if (fuseRegPp & 0x4000U)\r
+ hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
+ else if (fuseRegPp & 0x2000U)\r
+ hwFuseSts.maxPpOutPicWidthFuse = 720;\r
+ else if (fuseRegPp & 0x1000U)\r
+ hwFuseSts.maxPpOutPicWidthFuse = 352;\r
+ else\r
+ hwFuseSts.maxPpOutPicWidthFuse = 352;\r
+ hwFuseSts.ppConfigFuse = fuseRegPp;\r
+ } else {\r
+ hwFuseSts.ppSupportFuse = 0;\r
+ hwFuseSts.maxPpOutPicWidthFuse = 0;\r
+ hwFuseSts.ppConfigFuse = 0;\r
+ }\r
+ } else {\r
+ hwFuseSts.ppSupportFuse = 0;\r
+ hwFuseSts.maxPpOutPicWidthFuse = 0;\r
+ hwFuseSts.ppConfigFuse = 0;\r
+ }\r
\r
-#if !defined(CONFIG_ARCH_RK319X)\r
- /// invalidate fuse register value in rk319x vpu\r
- {\r
- VPUHwFuseStatus_t hwFuseSts;\r
- /* Decoder fuse configuration */\r
- u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
-\r
- hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
- hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
- hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
- hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
- hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
- hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
- hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
- hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
- hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
- hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
- hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
- hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
- hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
- hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
-\r
- /* check max. decoder output width */\r
-\r
- if (fuseReg & 0x8000U)\r
- hwFuseSts.maxDecPicWidthFuse = 1920;\r
- else if (fuseReg & 0x4000U)\r
- hwFuseSts.maxDecPicWidthFuse = 1280;\r
- else if (fuseReg & 0x2000U)\r
- hwFuseSts.maxDecPicWidthFuse = 720;\r
- else if (fuseReg & 0x1000U)\r
- hwFuseSts.maxDecPicWidthFuse = 352;\r
- else /* remove warning */\r
- hwFuseSts.maxDecPicWidthFuse = 352;\r
-\r
- hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
-\r
- /* Pp configuration */\r
- configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
-\r
- if ((configReg >> DWL_PP_E) & 0x01U) {\r
- dec->ppSupport = 1;\r
- dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
- /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
- dec->ppConfig = configReg;\r
- } else {\r
- dec->ppSupport = 0;\r
- dec->maxPpOutPicWidth = 0;\r
- dec->ppConfig = 0;\r
- }\r
-\r
- /* check the HW versio */\r
- if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
- /* Pp configuration */\r
- configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
-\r
- if ((configReg >> DWL_PP_E) & 0x01U) {\r
- /* Pp fuse configuration */\r
- u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
-\r
- if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
- hwFuseSts.ppSupportFuse = 1;\r
- /* check max. pp output width */\r
- if (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
- else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
- else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
- else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
- else hwFuseSts.maxPpOutPicWidthFuse = 352;\r
- hwFuseSts.ppConfigFuse = fuseRegPp;\r
- } else {\r
- hwFuseSts.ppSupportFuse = 0;\r
- hwFuseSts.maxPpOutPicWidthFuse = 0;\r
- hwFuseSts.ppConfigFuse = 0;\r
+ if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
+ dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
+ if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
+ dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
+ if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
+ if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
+ if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
+ if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
+ if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
+ dec->jpegSupport = JPEG_BASELINE;\r
+ if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
+ if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
+ if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
+ if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
+ if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
+ if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
+\r
+ /* check the pp config vs fuse status */\r
+ if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
+ u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
+ u32 alphaBlend = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
+ u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
+ u32 alphaBlendFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
+\r
+ if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
+ if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
+ }\r
+ if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
+ if (!hwFuseSts.refBufSupportFuse) dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
+ if (!hwFuseSts.rvSupportFuse) dec->rvSupport = RV_NOT_SUPPORTED;\r
+ if (!hwFuseSts.avsSupportFuse) dec->avsSupport = AVS_NOT_SUPPORTED;\r
+ if (!hwFuseSts.mvcSupportFuse) dec->mvcSupport = MVC_NOT_SUPPORTED;\r
}\r
- } else {\r
- hwFuseSts.ppSupportFuse = 0;\r
- hwFuseSts.maxPpOutPicWidthFuse = 0;\r
- hwFuseSts.ppConfigFuse = 0;\r
}\r
\r
- if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
- dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
- if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
- dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
- if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
- if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
- if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
- if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
- if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
- dec->jpegSupport = JPEG_BASELINE;\r
- if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
- if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
- if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
- if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
- if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
- if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
-\r
- /* check the pp config vs fuse status */\r
- if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
- u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
- u32 alphaBlend = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
- u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
- u32 alphaBlendFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
-\r
- if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
- if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
+ if (!cpu_is_rk3036()) {\r
+ configReg = pservice->enc_dev.hwregs[63];\r
+ enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
+ enc->h264Enabled = (configReg >> 27) & 1;\r
+ enc->mpeg4Enabled = (configReg >> 26) & 1;\r
+ enc->jpegEnabled = (configReg >> 25) & 1;\r
+ enc->vsEnabled = (configReg >> 24) & 1;\r
+ enc->rgbEnabled = (configReg >> 28) & 1;\r
+ /*enc->busType = (configReg >> 20) & 15;\r
+ enc->synthesisLanguage = (configReg >> 16) & 15;\r
+ enc->busWidth = (configReg >> 12) & 15;*/\r
+ enc->reg_size = pservice->reg_size;\r
+ enc->reserv[0] = enc->reserv[1] = 0;\r
}\r
- if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
- if (!hwFuseSts.refBufSupportFuse) dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
- if (!hwFuseSts.rvSupportFuse) dec->rvSupport = RV_NOT_SUPPORTED;\r
- if (!hwFuseSts.avsSupportFuse) dec->avsSupport = AVS_NOT_SUPPORTED;\r
- if (!hwFuseSts.mvcSupportFuse) dec->mvcSupport = MVC_NOT_SUPPORTED;\r
- }\r
- }\r
-#endif\r
- configReg = pservice->enc_dev.hwregs[63];\r
- enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
- enc->h264Enabled = (configReg >> 27) & 1;\r
- enc->mpeg4Enabled = (configReg >> 26) & 1;\r
- enc->jpegEnabled = (configReg >> 25) & 1;\r
- enc->vsEnabled = (configReg >> 24) & 1;\r
- enc->rgbEnabled = (configReg >> 28) & 1;\r
- //enc->busType = (configReg >> 20) & 15;\r
- //enc->synthesisLanguage = (configReg >> 16) & 15;\r
- //enc->busWidth = (configReg >> 12) & 15;\r
- enc->reg_size = pservice->reg_size;\r
- enc->reserv[0] = enc->reserv[1] = 0;\r
-\r
- pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926();\r
- if (pservice->auto_freq) {\r
- printk("vpu_service set to auto frequency mode\n");\r
- atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
+\r
+ pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();\r
+ if (pservice->auto_freq) {\r
+ pr_info("vpu_service set to auto frequency mode\n");\r
+ atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
+ }\r
+\r
+ pservice->bug_dec_addr = cpu_is_rk30xx();\r
+ } else {\r
+ if (cpu_is_rk3036() || cpu_is_rk312x())\r
+ dec->maxDecPicWidth = 1920;\r
+ else\r
+ dec->maxDecPicWidth = 4096;\r
+ /* disable frequency switch in hevc.*/\r
+ pservice->auto_freq = false;\r
}\r
- pservice->bug_dec_addr = cpu_is_rk30xx();\r
- //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
}\r
\r
static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
{\r
- struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
- vpu_device *dev = &pservice->dec_dev;\r
- u32 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
+ struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
+ vpu_device *dev = &pservice->dec_dev;\r
+ u32 raw_status;\r
+ u32 irq_status;\r
+\r
+ vcodec_enter_mode_nolock(pservice->dev_id, &pservice->reserved_mode);\r
+\r
+ irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
\r
pr_debug("dec_irq\n");\r
\r
}\r
\r
/* clear dec IRQ */\r
- if (pservice->hw_info->hw_id != HEVC_ID) {\r
- writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
- } else {\r
- /*writel(irq_status \r
- & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
- dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
-\r
- writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
- }\r
+ if (pservice->hw_info->hw_id != HEVC_ID)\r
+ writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
+ else\r
+ writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
atomic_add(1, &dev->irq_count_codec);\r
}\r
\r
- if (pservice->hw_info->hw_id != HEVC_ID) {\r
- irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
- if (irq_status & PP_INTERRUPT_BIT) {\r
- pr_debug("vdpu_isr pp %x\n", irq_status);\r
- /* clear pp IRQ */\r
- writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
- atomic_add(1, &dev->irq_count_pp);\r
- }\r
- }\r
+ if (pservice->hw_info->hw_id != HEVC_ID) {\r
+ irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
+ if (irq_status & PP_INTERRUPT_BIT) {\r
+ pr_debug("vdpu_isr pp %x\n", irq_status);\r
+ /* clear pp IRQ */\r
+ writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
+ atomic_add(1, &dev->irq_count_pp);\r
+ }\r
+ }\r
+\r
+ pservice->irq_status = raw_status;\r
\r
- pservice->irq_status = irq_status;\r
+ vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);\r
\r
return IRQ_WAKE_THREAD;\r
}\r
\r
static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
{\r
- struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
- vpu_device *dev = &pservice->dec_dev;\r
+ struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
+ vpu_device *dev = &pservice->dec_dev;\r
\r
mutex_lock(&pservice->lock);\r
if (atomic_read(&dev->irq_count_codec)) {\r
\r
static irqreturn_t vepu_irq(int irq, void *dev_id)\r
{\r
- //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
- struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
- vpu_device *dev = &pservice->enc_dev;\r
- u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
+ struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
+ vpu_device *dev = &pservice->enc_dev;\r
+ u32 irq_status;\r
+\r
+ vcodec_enter_mode_nolock(pservice->dev_id, &pservice->reserved_mode);\r
+ irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
\r
pr_debug("vepu_irq irq status %x\n", irq_status);\r
\r
(enc_end.tv_sec - enc_start.tv_sec) * 1000 +\r
(enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
#endif\r
-\r
if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
/* clear enc IRQ */\r
writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
atomic_add(1, &dev->irq_count_codec);\r
}\r
\r
+ pservice->irq_status = irq_status;\r
+\r
+ vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);\r
+\r
return IRQ_WAKE_THREAD;\r
}\r
\r
static irqreturn_t vepu_isr(int irq, void *dev_id)\r
{\r
- //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
- struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
- vpu_device *dev = &pservice->enc_dev;\r
+ struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
+ vpu_device *dev = &pservice->enc_dev;\r
\r
mutex_lock(&pservice->lock);\r
if (atomic_read(&dev->irq_count_codec)) {\r
\r
static int __init vcodec_service_init(void)\r
{\r
- int ret;\r
+ int ret;\r
\r
- if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
- pr_err("Platform device register failed (%d).\n", ret);\r
- return ret;\r
- }\r
+ if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
+ pr_err("Platform device register failed (%d).\n", ret);\r
+ return ret;\r
+ }\r
\r
#ifdef CONFIG_DEBUG_FS\r
- vcodec_debugfs_init();\r
+ vcodec_debugfs_init();\r
#endif\r
\r
- return ret;\r
+ return ret;\r
}\r
\r
static void __exit vcodec_service_exit(void)\r
{\r
#ifdef CONFIG_DEBUG_FS\r
- vcodec_debugfs_exit();\r
+ vcodec_debugfs_exit();\r
#endif\r
\r
platform_driver_unregister(&vcodec_driver);\r
\r
static int vcodec_debugfs_init()\r
{\r
- parent = debugfs_create_dir("vcodec", NULL);\r
- if (!parent)\r
- return -1;\r
+ parent = debugfs_create_dir("vcodec", NULL);\r
+ if (!parent)\r
+ return -1;\r
\r
- return 0;\r
+ return 0;\r
}\r
\r
static void vcodec_debugfs_exit()\r
{\r
- debugfs_remove(parent);\r
+ debugfs_remove(parent);\r
}\r
\r
static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
{\r
- return debugfs_create_dir(dirname, parent);\r
+ return debugfs_create_dir(dirname, parent);\r
}\r
\r
static int debug_vcodec_show(struct seq_file *s, void *unused)\r
{\r
struct vpu_service_info *pservice = s->private;\r
- unsigned int i, n;\r
+ unsigned int i, n;\r
vpu_reg *reg, *reg_tmp;\r
vpu_session *session, *session_tmp;\r
\r
mutex_lock(&pservice->lock);\r
vpu_service_power_on(pservice);\r
- if (pservice->hw_info->hw_id != HEVC_ID) {\r
- seq_printf(s, "\nENC Registers:\n");\r
- n = pservice->enc_dev.iosize >> 2;\r
- for (i = 0; i < n; i++) {\r
- seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
- }\r
- }\r
+ if (pservice->hw_info->hw_id != HEVC_ID) {\r
+ seq_printf(s, "\nENC Registers:\n");\r
+ n = pservice->enc_dev.iosize >> 2;\r
+ for (i = 0; i < n; i++) {\r
+ seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
+ }\r
+ }\r
seq_printf(s, "\nDEC Registers:\n");\r
n = pservice->dec_dev.iosize >> 2;\r
- for (i = 0; i < n; i++) {\r
+ for (i = 0; i < n; i++)\r
seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
- }\r
\r
seq_printf(s, "\nvpu service status:\n");\r
list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
- //seq_printf(s, "waiting reg set %d\n");\r
+ /*seq_printf(s, "waiting reg set %d\n");*/\r
list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
seq_printf(s, "waiting register set\n");\r
}\r
}\r
mutex_unlock(&pservice->lock);\r
\r
- return 0;\r
+ return 0;\r
}\r
\r
static int debug_vcodec_open(struct inode *inode, struct file *file)\r
\r
#endif\r
\r
-#if HEVC_TEST_ENABLE\r
+#if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
#include "hevc_test_inc/pps_00.h"\r
#include "hevc_test_inc/register_00.h"\r
#include "hevc_test_inc/rps_00.h"\r
\r
#include "hevc_test_inc/cabac.h"\r
\r
+extern struct ion_client *rockchip_ion_client_create(const char * name);\r
+\r
+static struct ion_client *ion_client = NULL;\r
+u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
+{\r
+ int size = (len+15) & (~15);\r
+ struct ion_handle *handle;\r
+ u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
+\r
+ if (ion_client == NULL)\r
+ ion_client = rockchip_ion_client_create("vcodec");\r
+\r
+ handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
+\r
+ ptr = ion_map_kernel(ion_client, handle);\r
+\r
+ ion_phys(ion_client, handle, phy, &size);\r
+\r
+ memcpy(ptr, tbl, len);\r
+\r
+ return ptr;\r
+}\r
+\r
+u8* get_align_ptr_no_copy(int len, u32 *phy)\r
+{\r
+ int size = (len+15) & (~15);\r
+ struct ion_handle *handle;\r
+ u8 *ptr;\r
+\r
+ if (ion_client == NULL)\r
+ ion_client = rockchip_ion_client_create("vcodec");\r
+\r
+ handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
+\r
+ ptr = ion_map_kernel(ion_client, handle);\r
+\r
+ ion_phys(ion_client, handle, phy, &size);\r
+\r
+ return ptr;\r
+}\r
+\r
#define TEST_CNT 2\r
static int hevc_test_case0(vpu_service_info *pservice)\r
{\r
- vpu_session session;\r
- vpu_reg *reg; \r
- unsigned long size = sizeof(register_00); // registers array length\r
- int testidx = 0;\r
- int ret = 0;\r
-\r
- u8 *pps_tbl[TEST_CNT];\r
- u8 *register_tbl[TEST_CNT];\r
- u8 *rps_tbl[TEST_CNT];\r
- u8 *scaling_list_tbl[TEST_CNT];\r
- u8 *stream_tbl[TEST_CNT];\r
-\r
- int stream_size[2];\r
-\r
- u32 phy_pps;\r
- u32 phy_rps;\r
- u32 phy_scl;\r
- u32 phy_str;\r
- u32 phy_yuv;\r
- u32 phy_cabac;\r
-\r
- u8 *pps;\r
- u8 *yuv;\r
- int i;\r
- \r
- pps_tbl[0] = pps_00;\r
- pps_tbl[1] = pps_01;\r
-\r
- register_tbl[0] = register_00;\r
- register_tbl[1] = register_01;\r
- \r
- rps_tbl[0] = rps_00;\r
- rps_tbl[1] = rps_01;\r
- \r
- scaling_list_tbl[0] = scaling_list_00;\r
- scaling_list_tbl[1] = scaling_list_01;\r
-\r
- stream_tbl[0] = stream_00;\r
- stream_tbl[1] = stream_01;\r
-\r
- stream_size[0] = sizeof(stream_00);\r
- stream_size[1] = sizeof(stream_01);\r
-\r
- // create session\r
- session.pid = current->pid;\r
- session.type = VPU_DEC;\r
- INIT_LIST_HEAD(&session.waiting);\r
+ vpu_session session;\r
+ vpu_reg *reg;\r
+ unsigned long size = 272;//sizeof(register_00); // registers array length\r
+ int testidx = 0;\r
+ int ret = 0;\r
+\r
+ u8 *pps_tbl[TEST_CNT];\r
+ u8 *register_tbl[TEST_CNT];\r
+ u8 *rps_tbl[TEST_CNT];\r
+ u8 *scaling_list_tbl[TEST_CNT];\r
+ u8 *stream_tbl[TEST_CNT];\r
+\r
+ int stream_size[2];\r
+ int pps_size[2];\r
+ int rps_size[2];\r
+ int scl_size[2];\r
+ int cabac_size[2];\r
+\r
+ u32 phy_pps;\r
+ u32 phy_rps;\r
+ u32 phy_scl;\r
+ u32 phy_str;\r
+ u32 phy_yuv;\r
+ u32 phy_ref;\r
+ u32 phy_cabac;\r
+\r
+ volatile u8 *stream_buf;\r
+ volatile u8 *pps_buf;\r
+ volatile u8 *rps_buf;\r
+ volatile u8 *scl_buf;\r
+ volatile u8 *yuv_buf;\r
+ volatile u8 *cabac_buf;\r
+ volatile u8 *ref_buf;\r
+\r
+ u8 *pps;\r
+ u8 *yuv[2];\r
+ int i;\r
+\r
+ pps_tbl[0] = pps_00;\r
+ pps_tbl[1] = pps_01;\r
+\r
+ register_tbl[0] = register_00;\r
+ register_tbl[1] = register_01;\r
+\r
+ rps_tbl[0] = rps_00;\r
+ rps_tbl[1] = rps_01;\r
+\r
+ scaling_list_tbl[0] = scaling_list_00;\r
+ scaling_list_tbl[1] = scaling_list_01;\r
+\r
+ stream_tbl[0] = stream_00;\r
+ stream_tbl[1] = stream_01;\r
+\r
+ stream_size[0] = sizeof(stream_00);\r
+ stream_size[1] = sizeof(stream_01);\r
+\r
+ pps_size[0] = sizeof(pps_00);\r
+ pps_size[1] = sizeof(pps_01);\r
+\r
+ rps_size[0] = sizeof(rps_00);\r
+ rps_size[1] = sizeof(rps_01);\r
+\r
+ scl_size[0] = sizeof(scaling_list_00);\r
+ scl_size[1] = sizeof(scaling_list_01);\r
+\r
+ cabac_size[0] = sizeof(Cabac_table);\r
+ cabac_size[1] = sizeof(Cabac_table);\r
+\r
+ /* create session */\r
+ session.pid = current->pid;\r
+ session.type = VPU_DEC;\r
+ INIT_LIST_HEAD(&session.waiting);\r
INIT_LIST_HEAD(&session.running);\r
INIT_LIST_HEAD(&session.done);\r
INIT_LIST_HEAD(&session.list_session);\r
atomic_set(&session.task_running, 0);\r
list_add_tail(&session.list_session, &pservice->session);\r
\r
- while (testidx < TEST_CNT) {\r
- // create registers\r
- reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
- if (NULL == reg) {\r
- pr_err("error: kmalloc fail in reg_init\n");\r
- return -1;\r
- }\r
-\r
- if (size > pservice->reg_size) {\r
- printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
- size = pservice->reg_size;\r
- }\r
- reg->session = &session;\r
- reg->type = session.type;\r
- reg->size = size;\r
- reg->freq = VPU_FREQ_DEFAULT;\r
- reg->reg = (unsigned long *)®[1];\r
- INIT_LIST_HEAD(®->session_link);\r
- INIT_LIST_HEAD(®->status_link);\r
-\r
- pps = kmalloc(sizeof(pps_00), GFP_KERNEL);\r
- yuv = kzalloc(256*256*3/2, GFP_KERNEL);\r
- memcpy(pps, pps_tbl[testidx], sizeof(pps_00));\r
-\r
- // TODO: stuff registers\r
- memcpy(®->reg[0], register_tbl[testidx], sizeof(register_00));\r
-\r
- // TODO: replace reigster address\r
- phy_pps = virt_to_phys(pps);\r
- phy_rps = virt_to_phys(rps_tbl[testidx]);\r
- phy_scl = virt_to_phys(scaling_list_tbl[testidx]);\r
- phy_str = virt_to_phys(stream_tbl[testidx]);\r
- phy_yuv = virt_to_phys(yuv);\r
- phy_cabac = virt_to_phys(Cabac_table);\r
-\r
- for (i=0; i<64; i++) {\r
- u32 scaling_offset;\r
- u32 tmp;\r
-\r
- scaling_offset = (u32)pps[i*80+74];\r
- scaling_offset += (u32)pps[i*80+75] << 8;\r
- scaling_offset += (u32)pps[i*80+76] << 16;\r
- scaling_offset += (u32)pps[i*80+77] << 24;\r
-\r
- tmp = phy_scl + scaling_offset;\r
-\r
- pps[i*80+74] = tmp & 0xff;\r
- pps[i*80+75] = (tmp >> 8) & 0xff;\r
- pps[i*80+76] = (tmp >> 16) & 0xff;\r
- pps[i*80+77] = (tmp >> 24) & 0xff;\r
- }\r
-\r
- dmac_flush_range(&pps[0], &pps[sizeof(pps_00) - 1]);\r
- outer_flush_range(phy_pps, phy_pps + sizeof(pps_00) - 1);\r
-\r
- printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
-\r
- reg->reg[4] = phy_str;\r
- reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
- reg->reg[6] = phy_cabac;\r
- reg->reg[7] = phy_yuv;\r
- reg->reg[42] = phy_pps;\r
- reg->reg[43] = phy_rps;\r
-\r
- mutex_lock(&pservice->lock);\r
- list_add_tail(®->status_link, &pservice->waiting);\r
- list_add_tail(®->session_link, &session.waiting);\r
- mutex_unlock(&pservice->lock);\r
-\r
- printk("%s %d %p\n", __func__, __LINE__, pservice);\r
-\r
- // stuff hardware\r
- try_set_reg(pservice);\r
-\r
- // wait for result\r
- ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
- if (!list_empty(&session.done)) {\r
- if (ret < 0) {\r
- pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
- }\r
- ret = 0;\r
- } else {\r
- if (unlikely(ret < 0)) {\r
- pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
- } else if (0 == ret) {\r
- pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
- ret = -ETIMEDOUT;\r
- }\r
- }\r
- if (ret < 0) {\r
- int task_running = atomic_read(&session.task_running);\r
- int n;\r
- mutex_lock(&pservice->lock);\r
- vpu_service_dump(pservice);\r
- if (task_running) {\r
- atomic_set(&session.task_running, 0);\r
- atomic_sub(task_running, &pservice->total_running);\r
- printk("%d task is running but not return, reset hardware...", task_running);\r
- vpu_reset(pservice);\r
- printk("done\n");\r
- }\r
- vpu_service_session_clear(pservice, &session);\r
- mutex_unlock(&pservice->lock);\r
-\r
- printk("\nDEC Registers:\n");\r
- n = pservice->dec_dev.iosize >> 2;\r
- for (i=0; i<n; i++) {\r
- printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
- }\r
-\r
- pr_err("test index %d failed\n", testidx);\r
- kfree(pps);\r
- kfree(yuv);\r
- break;\r
- } else {\r
- pr_info("test index %d success\n", testidx);\r
-\r
- vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
-\r
- for (i=0; i<68; i++) {\r
- if (i % 4 == 0) {\r
- printk("%02d: ", i);\r
- }\r
- printk("%08x ", reg->reg[i]);\r
- if ((i+1) % 4 == 0) {\r
- printk("\n");\r
- }\r
- }\r
-\r
- testidx++;\r
- }\r
-\r
- reg_deinit(pservice, reg);\r
- kfree(pps);\r
- kfree(yuv);\r
- }\r
-\r
- return 0;\r
+ yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
+ yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
+\r
+ while (testidx < TEST_CNT) {\r
+ /* create registers */\r
+ reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
+ if (NULL == reg) {\r
+ pr_err("error: kmalloc fail in reg_init\n");\r
+ return -1;\r
+ }\r
+\r
+ if (size > pservice->reg_size) {\r
+ printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
+ size = pservice->reg_size;\r
+ }\r
+ reg->session = &session;\r
+ reg->type = session.type;\r
+ reg->size = size;\r
+ reg->freq = VPU_FREQ_DEFAULT;\r
+ reg->reg = (unsigned long *)®[1];\r
+ INIT_LIST_HEAD(®->session_link);\r
+ INIT_LIST_HEAD(®->status_link);\r
+\r
+ /* TODO: stuff registers */\r
+ memcpy(®->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
+\r
+ stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
+ pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
+ rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
+ scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
+ cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
+\r
+ pps = pps_buf;\r
+\r
+ /* TODO: replace reigster address */\r
+ for (i=0; i<64; i++) {\r
+ u32 scaling_offset;\r
+ u32 tmp;\r
+\r
+ scaling_offset = (u32)pps[i*80+74];\r
+ scaling_offset += (u32)pps[i*80+75] << 8;\r
+ scaling_offset += (u32)pps[i*80+76] << 16;\r
+ scaling_offset += (u32)pps[i*80+77] << 24;\r
+\r
+ tmp = phy_scl + scaling_offset;\r
+\r
+ pps[i*80+74] = tmp & 0xff;\r
+ pps[i*80+75] = (tmp >> 8) & 0xff;\r
+ pps[i*80+76] = (tmp >> 16) & 0xff;\r
+ pps[i*80+77] = (tmp >> 24) & 0xff;\r
+ }\r
+\r
+ printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",\r
+ __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
+\r
+ reg->reg[1] = 0x21;\r
+ reg->reg[4] = phy_str;\r
+ reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
+ reg->reg[6] = phy_cabac;\r
+ reg->reg[7] = testidx?phy_ref:phy_yuv;\r
+ reg->reg[42] = phy_pps;\r
+ reg->reg[43] = phy_rps;\r
+ for (i = 10; i <= 24; i++)\r
+ reg->reg[i] = phy_yuv;\r
+\r
+ mutex_lock(&pservice->lock);\r
+ list_add_tail(®->status_link, &pservice->waiting);\r
+ list_add_tail(®->session_link, &session.waiting);\r
+ mutex_unlock(&pservice->lock);\r
+\r
+ printk("%s %d %p\n", __func__, __LINE__, pservice);\r
+\r
+ /* stuff hardware */\r
+ try_set_reg(pservice);\r
+\r
+ /* wait for result */\r
+ ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
+ if (!list_empty(&session.done)) {\r
+ if (ret < 0)\r
+ pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
+ ret = 0;\r
+ } else {\r
+ if (unlikely(ret < 0)) {\r
+ pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
+ } else if (0 == ret) {\r
+ pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
+ ret = -ETIMEDOUT;\r
+ }\r
+ }\r
+ if (ret < 0) {\r
+ int task_running = atomic_read(&session.task_running);\r
+ int n;\r
+ mutex_lock(&pservice->lock);\r
+ vpu_service_dump(pservice);\r
+ if (task_running) {\r
+ atomic_set(&session.task_running, 0);\r
+ atomic_sub(task_running, &pservice->total_running);\r
+ printk("%d task is running but not return, reset hardware...", task_running);\r
+ vpu_reset(pservice);\r
+ printk("done\n");\r
+ }\r
+ vpu_service_session_clear(pservice, &session);\r
+ mutex_unlock(&pservice->lock);\r
+\r
+ printk("\nDEC Registers:\n");\r
+ n = pservice->dec_dev.iosize >> 2;\r
+ for (i=0; i<n; i++)\r
+ printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
+\r
+ pr_err("test index %d failed\n", testidx);\r
+ break;\r
+ } else {\r
+ pr_info("test index %d success\n", testidx);\r
+\r
+ vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
+\r
+ for (i=0; i<68; i++) {\r
+ if (i % 4 == 0)\r
+ printk("%02d: ", i);\r
+ printk("%08x ", reg->reg[i]);\r
+ if ((i+1) % 4 == 0)\r
+ printk("\n");\r
+ }\r
+\r
+ testidx++;\r
+ }\r
+\r
+ reg_deinit(pservice, reg);\r
+ }\r
+\r
+ return 0;\r
}\r
\r
#endif\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff