Implement ISD::VAARG lowering on PPC32.

[oota-llvm.git] / Makefile.rules

diff --git a/Makefile.rules b/Makefile.rules
index 98c72c0d055f9501c6faa3a25258a0c295cacb84..2acadd84003898f514b1f9ceb6a8beea0061b3ee 100644 (file)
--- a/Makefile.rules
+++ b/Makefile.rules
@@ -1725,15 +1725,20 @@ $(ObjDir)/%GenRegisterNames.inc.tmp : %.td $(ObjDir)/.dir
        $(Echo) "Building $(<F) register names with tblgen"
        $(Verb) $(TableGen) -gen-register-enums -o $(call SYSPATH, $@) $<
 
+$(TARGET:%=$(ObjDir)/%GenRegisterDesc.inc.tmp): \
+$(ObjDir)/%GenRegisterDesc.inc.tmp : %.td $(ObjDir)/.dir
+       $(Echo) "Building $(<F) register descriptions with tblgen"
+       $(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
+
 $(TARGET:%=$(ObjDir)/%GenRegisterInfo.h.inc.tmp): \
 $(ObjDir)/%GenRegisterInfo.h.inc.tmp : %.td $(ObjDir)/.dir
        $(Echo) "Building $(<F) register information header with tblgen"
-       $(Verb) $(TableGen) -gen-register-desc-header -o $(call SYSPATH, $@) $<
+       $(Verb) $(TableGen) -gen-register-info-header -o $(call SYSPATH, $@) $<
 
 $(TARGET:%=$(ObjDir)/%GenRegisterInfo.inc.tmp): \
 $(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir
        $(Echo) "Building $(<F) register info implementation with tblgen"
-       $(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
+       $(Verb) $(TableGen) -gen-register-info -o $(call SYSPATH, $@) $<
 
 $(TARGET:%=$(ObjDir)/%GenInstrNames.inc.tmp): \
 $(ObjDir)/%GenInstrNames.inc.tmp : %.td $(ObjDir)/.dir