E: evan.cheng@apple.com
D: ARM and X86 backends
D: Instruction scheduler improvements
+D: Register allocator improvements
D: Loop optimizer improvements
D: Target-independent code generator improvements
E: djg@cray.com
D: Miscellaneous bug fixes
+N: David Greene
+E: greened@obbligato.org
+D: Miscellaneous bug fixes
+D: Register allocation refactoring
+
N: Paolo Invernizzi
E: arathorn@fastwebnet.it
D: Visual C++ compatibility fixes
E: nicholas@mxc.ca
D: PredicateSimplifier pass
+N: Bruno Cardoso Lopes
+E: bruno.cardoso@gmail.com
+W: http://www.brunocardoso.org
+D: The Mips backend
+
N: Duraid Madina
E: duraid@octopus.com.au
W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
N: Bill Wendling
E: isanbard@gmail.com
W: http://web.mac.com/bwendling/
-D: The `Lower Setjmp/Longjmp' pass, improvements to the -lowerswitch pass.
+D: MMX & SSSE3 instructions
+D: SPEC2006 support