+ MipsGOTParser<ELFT> GOTParser(Obj, dynamic_table(), W);
+ GOTParser.parseGOT();
+ GOTParser.parsePLT();
+}
+
+static const EnumEntry<unsigned> ElfMipsISAExtType[] = {
+ {"None", Mips::AFL_EXT_NONE},
+ {"Broadcom SB-1", Mips::AFL_EXT_SB1},
+ {"Cavium Networks Octeon", Mips::AFL_EXT_OCTEON},
+ {"Cavium Networks Octeon2", Mips::AFL_EXT_OCTEON2},
+ {"Cavium Networks OcteonP", Mips::AFL_EXT_OCTEONP},
+ {"Cavium Networks Octeon3", Mips::AFL_EXT_OCTEON3},
+ {"LSI R4010", Mips::AFL_EXT_4010},
+ {"Loongson 2E", Mips::AFL_EXT_LOONGSON_2E},
+ {"Loongson 2F", Mips::AFL_EXT_LOONGSON_2F},
+ {"Loongson 3A", Mips::AFL_EXT_LOONGSON_3A},
+ {"MIPS R4650", Mips::AFL_EXT_4650},
+ {"MIPS R5900", Mips::AFL_EXT_5900},
+ {"MIPS R10000", Mips::AFL_EXT_10000},
+ {"NEC VR4100", Mips::AFL_EXT_4100},
+ {"NEC VR4111/VR4181", Mips::AFL_EXT_4111},
+ {"NEC VR4120", Mips::AFL_EXT_4120},
+ {"NEC VR5400", Mips::AFL_EXT_5400},
+ {"NEC VR5500", Mips::AFL_EXT_5500},
+ {"RMI Xlr", Mips::AFL_EXT_XLR},
+ {"Toshiba R3900", Mips::AFL_EXT_3900}
+};
+
+static const EnumEntry<unsigned> ElfMipsASEFlags[] = {
+ {"DSP", Mips::AFL_ASE_DSP},
+ {"DSPR2", Mips::AFL_ASE_DSPR2},
+ {"Enhanced VA Scheme", Mips::AFL_ASE_EVA},
+ {"MCU", Mips::AFL_ASE_MCU},
+ {"MDMX", Mips::AFL_ASE_MDMX},
+ {"MIPS-3D", Mips::AFL_ASE_MIPS3D},
+ {"MT", Mips::AFL_ASE_MT},
+ {"SmartMIPS", Mips::AFL_ASE_SMARTMIPS},
+ {"VZ", Mips::AFL_ASE_VIRT},
+ {"MSA", Mips::AFL_ASE_MSA},
+ {"MIPS16", Mips::AFL_ASE_MIPS16},
+ {"microMIPS", Mips::AFL_ASE_MICROMIPS},
+ {"XPA", Mips::AFL_ASE_XPA}
+};
+
+static const EnumEntry<unsigned> ElfMipsFpABIType[] = {
+ {"Hard or soft float", Mips::Val_GNU_MIPS_ABI_FP_ANY},
+ {"Hard float (double precision)", Mips::Val_GNU_MIPS_ABI_FP_DOUBLE},
+ {"Hard float (single precision)", Mips::Val_GNU_MIPS_ABI_FP_SINGLE},
+ {"Soft float", Mips::Val_GNU_MIPS_ABI_FP_SOFT},
+ {"Hard float (MIPS32r2 64-bit FPU 12 callee-saved)",
+ Mips::Val_GNU_MIPS_ABI_FP_OLD_64},
+ {"Hard float (32-bit CPU, Any FPU)", Mips::Val_GNU_MIPS_ABI_FP_XX},
+ {"Hard float (32-bit CPU, 64-bit FPU)", Mips::Val_GNU_MIPS_ABI_FP_64},
+ {"Hard float compat (32-bit CPU, 64-bit FPU)",
+ Mips::Val_GNU_MIPS_ABI_FP_64A}
+};
+
+static const EnumEntry<unsigned> ElfMipsFlags1[] {
+ {"ODDSPREG", Mips::AFL_FLAGS1_ODDSPREG},
+};
+
+static int getMipsRegisterSize(uint8_t Flag) {
+ switch (Flag) {
+ case Mips::AFL_REG_NONE:
+ return 0;
+ case Mips::AFL_REG_32:
+ return 32;
+ case Mips::AFL_REG_64:
+ return 64;
+ case Mips::AFL_REG_128:
+ return 128;
+ default:
+ return -1;