+define i32 @test1(i32 %A) {
+; CHECK: @test1
+ %B = mul i32 %A, 1 ; <i32> [#uses=1]
+ ret i32 %B
+; CHECK: ret i32 %A
+}
+
+define i32 @test2(i32 %A) {
+; CHECK: @test2
+ ; Should convert to an add instruction
+ %B = mul i32 %A, 2 ; <i32> [#uses=1]
+ ret i32 %B
+; CHECK: shl i32 %A, 1
+}
+
+define i32 @test3(i32 %A) {
+; CHECK: @test3
+ ; This should disappear entirely
+ %B = mul i32 %A, 0 ; <i32> [#uses=1]
+ ret i32 %B
+; CHECK: ret i32 0
+}
+
+define double @test4(double %A) {
+; CHECK: @test4
+ ; This is safe for FP
+ %B = fmul double 1.000000e+00, %A ; <double> [#uses=1]
+ ret double %B
+; CHECK: ret double %A
+}
+
+define i32 @test5(i32 %A) {
+; CHECK: @test5
+ %B = mul i32 %A, 8 ; <i32> [#uses=1]
+ ret i32 %B
+; CHECK: shl i32 %A, 3
+}
+
+define i8 @test6(i8 %A) {
+; CHECK: @test6
+ %B = mul i8 %A, 8 ; <i8> [#uses=1]
+ %C = mul i8 %B, 8 ; <i8> [#uses=1]
+ ret i8 %C
+; CHECK: shl i8 %A, 6
+}
+
+define i32 @test7(i32 %i) {
+; CHECK: @test7
+ %tmp = mul i32 %i, -1 ; <i32> [#uses=1]
+ ret i32 %tmp
+; CHECK: sub i32 0, %i
+}
+
+define i64 @test8(i64 %i) {
+; CHECK: @test8
+ %j = mul i64 %i, -1 ; <i64> [#uses=1]
+ ret i64 %j
+; CHECK: sub i64 0, %i
+}
+
+define i32 @test9(i32 %i) {
+; CHECK: @test9
+ %j = mul i32 %i, -1 ; <i32> [#uses=1]
+ ret i32 %j
+; CHECK: sub i32 0, %i
+}
+
+define i32 @test10(i32 %a, i32 %b) {
+; CHECK: @test10
+ %c = icmp slt i32 %a, 0 ; <i1> [#uses=1]
+ %d = zext i1 %c to i32 ; <i32> [#uses=1]
+ ; e = b & (a >> 31)
+ %e = mul i32 %d, %b ; <i32> [#uses=1]
+ ret i32 %e
+; CHECK: [[TEST10:%.*]] = ashr i32 %a, 31
+; CHECK-NEXT: %e = and i32 [[TEST10]], %b
+; CHECK-NEXT: ret i32 %e
+}
+
+define i32 @test11(i32 %a, i32 %b) {
+; CHECK: @test11
+ %c = icmp sle i32 %a, -1 ; <i1> [#uses=1]
+ %d = zext i1 %c to i32 ; <i32> [#uses=1]
+ ; e = b & (a >> 31)
+ %e = mul i32 %d, %b ; <i32> [#uses=1]
+ ret i32 %e
+; CHECK: [[TEST11:%.*]] = ashr i32 %a, 31
+; CHECK-NEXT: %e = and i32 [[TEST11]], %b
+; CHECK-NEXT: ret i32 %e
+}