projects
/
oota-llvm.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
[WebAssembly] Fix legalization of shift operators on large integer types.
[oota-llvm.git]
/
test
/
CodeGen
/
Thumb2
/
thumb2-spill-q.ll
diff --git
a/test/CodeGen/Thumb2/thumb2-spill-q.ll
b/test/CodeGen/Thumb2/thumb2-spill-q.ll
index 94f472593b3c250717df7de4b3d7afaea981e2d8..f408242ea01fa7c56de84f953bee236b6cf95015 100644
(file)
--- a/
test/CodeGen/Thumb2/thumb2-spill-q.ll
+++ b/
test/CodeGen/Thumb2/thumb2-spill-q.ll
@@
-7,43
+7,43
@@
%quux = type { i32 (...)**, %baz*, i32 }
%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
%quux = type { i32 (...)**, %baz*, i32 }
%quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo }
-declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
+declare <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8*, i32) nounwind readonly
define void @aaa(%quuz* %this, i8* %block) {
; CHECK-LABEL: aaa:
define void @aaa(%quuz* %this, i8* %block) {
; CHECK-LABEL: aaa:
-; CHECK: b
ic r4, r4, #15
+; CHECK: b
fc r4, #0, #4
; CHECK: vst1.64 {{.*}}[{{.*}}:128]
; CHECK: vld1.64 {{.*}}[{{.*}}:128]
entry:
%aligned_vec = alloca <4 x float>, align 16
%"alloca point" = bitcast i32 0 to i32
%vecptr = bitcast <4 x float>* %aligned_vec to i8*
; CHECK: vst1.64 {{.*}}[{{.*}}:128]
; CHECK: vld1.64 {{.*}}[{{.*}}:128]
entry:
%aligned_vec = alloca <4 x float>, align 16
%"alloca point" = bitcast i32 0 to i32
%vecptr = bitcast <4 x float>* %aligned_vec to i8*
- %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %vecptr, i32 1) nounwind
+ %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* %vecptr, i32 1) nounwind
store float 6.300000e+01, float* undef, align 4
store float 6.300000e+01, float* undef, align 4
- %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
+ %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
- %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
+ %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
+ %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
+ %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
+ %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
+ %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
+ %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
+ %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %ld9 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
+ %ld9 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %ld10 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
+ %ld10 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %ld11 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
+ %ld11 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
+ %ld12 = call <4 x float> @llvm.arm.neon.vld1.v4f32
.p0i8
(i8* undef, i32 1) nounwind
store float 0.000000e+00, float* undef, align 4
store float 0.000000e+00, float* undef, align 4
- %val173 = load <4 x float>* undef ; <<4 x float>> [#uses=1]
+ %val173 = load <4 x float>
, <4 x float>
* undef ; <<4 x float>> [#uses=1]
br label %bb4
bb4: ; preds = %bb193, %entry
br label %bb4
bb4: ; preds = %bb193, %entry