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XFAIL test/CodeGen/Generic/MachineBranchProb.ll on Hexagon (PR23377)
[oota-llvm.git]
/
test
/
CodeGen
/
Mips
/
rotate.ll
diff --git
a/test/CodeGen/Mips/rotate.ll
b/test/CodeGen/Mips/rotate.ll
index 4f3cfb7df41c5a65699e6285b36dd09031c32677..70eff6e224d075fb8662b0640c81ee28c3e73331 100644
(file)
--- a/
test/CodeGen/Mips/rotate.ll
+++ b/
test/CodeGen/Mips/rotate.ll
@@
-1,6
+1,8
@@
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16
; CHECK: rotrv $2, $4
; CHECK: rotrv $2, $4
+; mips16: .ent rot0
define i32 @rot0(i32 %a, i32 %b) nounwind readnone {
entry:
%shl = shl i32 %a, %b
define i32 @rot0(i32 %a, i32 %b) nounwind readnone {
entry:
%shl = shl i32 %a, %b
@@
-11,6
+13,7
@@
entry:
}
; CHECK: rotr $2, $4, 22
}
; CHECK: rotr $2, $4, 22
+; mips16: .ent rot1
define i32 @rot1(i32 %a) nounwind readnone {
entry:
%shl = shl i32 %a, 10
define i32 @rot1(i32 %a) nounwind readnone {
entry:
%shl = shl i32 %a, 10
@@
-20,6
+23,7
@@
entry:
}
; CHECK: rotrv $2, $4, $5
}
; CHECK: rotrv $2, $4, $5
+; mips16: .ent rot2
define i32 @rot2(i32 %a, i32 %b) nounwind readnone {
entry:
%shr = lshr i32 %a, %b
define i32 @rot2(i32 %a, i32 %b) nounwind readnone {
entry:
%shr = lshr i32 %a, %b
@@
-30,6
+34,7
@@
entry:
}
; CHECK: rotr $2, $4, 10
}
; CHECK: rotr $2, $4, 10
+; mips16: .ent rot3
define i32 @rot3(i32 %a) nounwind readnone {
entry:
%shr = lshr i32 %a, 10
define i32 @rot3(i32 %a) nounwind readnone {
entry:
%shr = lshr i32 %a, 10