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[ARM] Fix MachO CPU Subtype selection
[oota-llvm.git]
/
test
/
CodeGen
/
ARM
/
fast-isel-pic.ll
diff --git
a/test/CodeGen/ARM/fast-isel-pic.ll
b/test/CodeGen/ARM/fast-isel-pic.ll
index 392a845d2cc3b8282b8bce7df918f53c4fc6d290..70e15daaca62a443c06e85ca326e5afa40902274 100644
(file)
--- a/
test/CodeGen/ARM/fast-isel-pic.ll
+++ b/
test/CodeGen/ARM/fast-isel-pic.ll
@@
-1,6
+1,8
@@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
@g = global i32 0, align 4
@g = global i32 0, align 4
@@
-10,6
+12,10
@@
entry:
; THUMB: movw [[reg0:r[0-9]+]],
; THUMB: movt [[reg0]],
; THUMB: add [[reg0]], pc
; THUMB: movw [[reg0:r[0-9]+]],
; THUMB: movt [[reg0]],
; THUMB: add [[reg0]], pc
+; THUMB-ELF: LoadGV
+; THUMB-ELF: ldr r[[reg0:[0-9]+]],
+; THUMB-ELF: ldr r[[reg1:[0-9]+]],
+; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]]
; ARM: LoadGV
; ARM: ldr [[reg1:r[0-9]+]],
; ARM: add [[reg1]], pc, [[reg1]]
; ARM: LoadGV
; ARM: ldr [[reg1:r[0-9]+]],
; ARM: add [[reg1]], pc, [[reg1]]
@@
-17,7
+23,13
@@
entry:
; ARMv7: movw [[reg2:r[0-9]+]],
; ARMv7: movt [[reg2]],
; ARMv7: add [[reg2]], pc, [[reg2]]
; ARMv7: movw [[reg2:r[0-9]+]],
; ARMv7: movt [[reg2]],
; ARMv7: add [[reg2]], pc, [[reg2]]
- %tmp = load i32* @g
+; ARMv7-ELF: LoadGV
+; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
+; ARMv7-ELF: .LPC
+; ARMv7-ELF-NEXT: add r[[reg2]], pc
+; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
+; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
+ %tmp = load i32, i32* @g
ret i32 %tmp
}
ret i32 %tmp
}
@@
-30,6
+42,10
@@
entry:
; THUMB: movt r[[reg3]],
; THUMB: add r[[reg3]], pc
; THUMB: ldr r[[reg3]], [r[[reg3]]]
; THUMB: movt r[[reg3]],
; THUMB: add r[[reg3]], pc
; THUMB: ldr r[[reg3]], [r[[reg3]]]
+; THUMB-ELF: LoadIndirectSymbol
+; THUMB-ELF: ldr r[[reg3:[0-9]+]],
+; THUMB-ELF: ldr r[[reg4:[0-9]+]],
+; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
; ARM: LoadIndirectSymbol
; ARM: ldr [[reg4:r[0-9]+]],
; ARM: ldr [[reg4]], [pc, [[reg4]]]
; ARM: LoadIndirectSymbol
; ARM: ldr [[reg4:r[0-9]+]],
; ARM: ldr [[reg4]], [pc, [[reg4]]]
@@
-38,6
+54,12
@@
entry:
; ARMv7: movt r[[reg5]],
; ARMv7: add r[[reg5]], pc, r[[reg5]]
; ARMv7: ldr r[[reg5]], [r[[reg5]]]
; ARMv7: movt r[[reg5]],
; ARMv7: add r[[reg5]], pc, r[[reg5]]
; ARMv7: ldr r[[reg5]], [r[[reg5]]]
- %tmp = load i32* @i
+; ARMv7-ELF: LoadIndirectSymbol
+; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
+; ARMv7-ELF: .LPC
+; ARMv7-ELF-NEXT: add r[[reg5]], pc
+; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
+; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
+ %tmp = load i32, i32* @i
ret i32 %tmp
}
ret i32 %tmp
}