+
+; Another test that exercises the AND/TST peephole optimization and also
+; generates a predicated ANDS instruction. Check that the predicate is printed
+; after the "S" modifier on the instruction.
+
+%struct.S = type { i8* (i8*)*, [1 x i8] }
+
+; ARM-LABEL: bar:
+; THUMB-LABEL: bar:
+; T2-LABEL: bar:
+; V8-LABEL: bar:
+define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
+entry:
+ %0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0
+ %1 = load i8, i8* %0, align 1
+ %2 = zext i8 %1 to i32
+; ARM: ands
+; THUMB: ands
+; T2: ands
+; V8: ands
+; V8-NEXT: beq
+ %3 = and i32 %2, 112
+ %4 = icmp eq i32 %3, 0
+ br i1 %4, label %return, label %bb
+
+bb: ; preds = %entry
+; V8-NEXT: %bb
+ %5 = getelementptr inbounds %struct.S, %struct.S* %y, i32 0, i32 1, i32 0
+ %6 = load i8, i8* %5, align 1
+ %7 = zext i8 %6 to i32
+; ARM: andsne
+; THUMB: ands
+; T2: andsne
+; V8: ands
+; V8-NEXT: beq
+ %8 = and i32 %7, 112
+ %9 = icmp eq i32 %8, 0
+ br i1 %9, label %return, label %bb2
+
+bb2: ; preds = %bb
+; V8-NEXT: %bb2
+; V8-NEXT: cmp
+; V8-NEXT: it ne
+; V8-NEXT: cmpne
+; V8-NEXT: bne
+ %10 = icmp eq i32 %3, 16
+ %11 = icmp eq i32 %8, 16
+ %or.cond = or i1 %10, %11
+ br i1 %or.cond, label %bb4, label %return
+
+bb4: ; preds = %bb2
+ %12 = ptrtoint %struct.S* %x to i32
+ %phitmp = trunc i32 %12 to i8
+ ret i8 %phitmp
+
+return: ; preds = %bb2, %bb, %entry
+ ret i8 1
+}
+
+
+; We were looking through multiple COPY instructions to find an AND we might
+; fold into a TST, but in doing so we changed the register being tested allowing
+; folding of unrelated tests (in this case, a TST against r1 was eliminated in
+; favour of an AND of r0).
+
+; ARM-LABEL: test_tst_assessment:
+; THUMB-LABEL: test_tst_assessment:
+; T2-LABEL: test_tst_assessment:
+; V8-LABEL: test_tst_assessment:
+define i32 @test_tst_assessment(i1 %lhs, i1 %rhs) {
+ %lhs32 = zext i1 %lhs to i32
+ %rhs32 = zext i1 %rhs to i32
+ %diff = sub nsw i32 %lhs32, %rhs32
+; ARM: tst r1, #1
+; THUMB: movs [[RTMP:r[0-9]+]], #1
+; THUMB: tst r1, [[RTMP]]
+; T2: tst.w r1, #1
+; V8: tst.w r1, #1
+ ret i32 %diff
+}
+
+!1 = !{!"branch_weights", i32 1, i32 1, i32 3, i32 2 }