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Target RegisterInfo: devirtualize TargetFrameLowering
[oota-llvm.git]
/
lib
/
Target
/
XCore
/
XCoreRegisterInfo.td
diff --git
a/lib/Target/XCore/XCoreRegisterInfo.td
b/lib/Target/XCore/XCoreRegisterInfo.td
index c3542304a4ec0875cb3dd1141807b6fd5dafd922..6694b2882acab9548ca3f3da056b8b7cd8f43542 100644
(file)
--- a/
lib/Target/XCore/XCoreRegisterInfo.td
+++ b/
lib/Target/XCore/XCoreRegisterInfo.td
@@
-1,4
+1,4
@@
-//===-
XCoreRegisterInfo.td - XCore Register defs -
---------*- tablegen -*-===//
+//===-
- XCoreRegisterInfo.td - XCore Register defs
---------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
//
// The LLVM Compiler Infrastructure
//
@@
-45,12
+45,15
@@
def LR : Ri<15, "lr">, DwarfRegNum<[15]>;
def GRRegs : RegisterClass<"XCore", [i32], 32,
// Return values and arguments
(add R0, R1, R2, R3,
def GRRegs : RegisterClass<"XCore", [i32], 32,
// Return values and arguments
(add R0, R1, R2, R3,
- // Not preserved across procedure calls
- R11,
// Callee save
// Callee save
- R4, R5, R6, R7, R8, R9, R10)>;
+ R4, R5, R6, R7, R8, R9, R10,
+ // Not preserved across procedure calls
+ R11)>;
// Reserved
// Reserved
-def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> {
+def RRegs : RegisterClass<"XCore", [i32], 32,
+ (add R0, R1, R2, R3,
+ R4, R5, R6, R7, R8, R9, R10,
+ R11, CP, DP, SP, LR)> {
let isAllocatable = 0;
}
let isAllocatable = 0;
}