case XCoreISD::BL : return "XCoreISD::BL";
case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
case XCoreISD::BL : return "XCoreISD::BL";
case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET";
case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN";
case XCoreISD::MEMBARRIER : return "XCoreISD::MEMBARRIER";
case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET";
case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN";
case XCoreISD::MEMBARRIER : return "XCoreISD::MEMBARRIER";
GA = getGlobalAddressWrapper(GA, GV, DAG);
// Handle the rest of the offset.
if (Offset != FoldedOffset) {
GA = getGlobalAddressWrapper(GA, GV, DAG);
// Handle the rest of the offset.
if (Offset != FoldedOffset) {
GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
}
return GA;
GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
}
return GA;
Constant *GA = ConstantExpr::getBitCast(const_cast<GlobalValue*>(GV), Ty);
Ty = Type::getInt32Ty(*DAG.getContext());
Constant *Idx = ConstantInt::get(Ty, Offset);
Constant *GA = ConstantExpr::getBitCast(const_cast<GlobalValue*>(GV), Ty);
Ty = Type::getInt32Ty(*DAG.getContext());
Constant *Idx = ConstantInt::get(Ty, Offset);
- Constant *GAI = ConstantExpr::getGetElementPtr(GA, Idx);
+ Constant *GAI = ConstantExpr::getGetElementPtr(
+ Type::getInt8Ty(*DAG.getContext()), GA, Idx);
- return DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), CP,
- MachinePointerInfo(), false, false, false, 0);
+ return DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL,
+ DAG.getEntryNode(), CP, MachinePointerInfo(), false,
+ false, false, 0);
- return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result);
+ return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, PtrVT, Result);
}
assert((NumEntries >> 31) == 0);
SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
}
assert((NumEntries >> 31) == 0);
SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
ScaledIndex);
}
return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
ScaledIndex);
}
lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, SDValue Base,
int64_t Offset, SelectionDAG &DAG) const
{
lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, SDValue Base,
int64_t Offset, SelectionDAG &DAG) const
{
- return DAG.getLoad(getPointerTy(), DL, Chain, Base, MachinePointerInfo(),
- false, false, false, 0);
+ return DAG.getLoad(PtrVT, DL, Chain, Base, MachinePointerInfo(), false,
+ false, false, 0);
}
// Lower to pair of consecutive word aligned loads plus some bit shifting.
int32_t HighOffset = RoundUpToAlignment(Offset, 4);
}
// Lower to pair of consecutive word aligned loads plus some bit shifting.
int32_t HighOffset = RoundUpToAlignment(Offset, 4);
HighOffset);
} else {
LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
HighOffset);
} else {
LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
- SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, MVT::i32);
- SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, MVT::i32);
+ SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, DL, MVT::i32);
+ SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, DL, MVT::i32);
- SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
- LowAddr, MachinePointerInfo(),
+ SDValue Low = DAG.getLoad(PtrVT, DL, Chain, LowAddr, MachinePointerInfo(),
- SDValue High = DAG.getLoad(getPointerTy(), DL, Chain,
- HighAddr, MachinePointerInfo(),
+ SDValue High = DAG.getLoad(PtrVT, DL, Chain, HighAddr, MachinePointerInfo(),
false, false, false, 0);
SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
false, false, false, 0);
SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
- unsigned ABIAlignment = getDataLayout()->
- getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
+ auto &TD = DAG.getDataLayout();
+ unsigned ABIAlignment = TD.getABITypeAlignment(
+ LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
LD->isVolatile(), LD->isNonTemporal(),
LD->isInvariant(), 2);
SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
LD->isVolatile(), LD->isNonTemporal(),
LD->isInvariant(), 2);
SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
HighAddr,
LD->getPointerInfo().getWithOffset(2),
MVT::i16, LD->isVolatile(),
LD->isNonTemporal(), LD->isInvariant(), 2);
SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
HighAddr,
LD->getPointerInfo().getWithOffset(2),
MVT::i16, LD->isVolatile(),
LD->isNonTemporal(), LD->isInvariant(), 2);
SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
High.getValue(1));
SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
High.getValue(1));
- CLI.setDebugLoc(DL).setChain(Chain)
- .setCallee(CallingConv::C, IntPtrTy,
- DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
- std::move(Args), 0);
+ CLI.setDebugLoc(DL).setChain(Chain).setCallee(
+ CallingConv::C, IntPtrTy,
+ DAG.getExternalSymbol("__misaligned_load",
+ getPointerTy(DAG.getDataLayout())),
+ std::move(Args), 0);
std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
SDValue Ops[] = { CallResult.first, CallResult.second };
std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
SDValue Ops[] = { CallResult.first, CallResult.second };
- unsigned ABIAlignment = getDataLayout()->
- getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
+ unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(
+ ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
if (ST->getAlignment() == 2) {
SDValue Low = Value;
SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
if (ST->getAlignment() == 2) {
SDValue Low = Value;
SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
ST->getPointerInfo(), MVT::i16,
ST->isVolatile(), ST->isNonTemporal(),
2);
SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
ST->getPointerInfo(), MVT::i16,
ST->isVolatile(), ST->isNonTemporal(),
2);
SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
ST->getPointerInfo().getWithOffset(2),
MVT::i16, ST->isVolatile(),
SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
ST->getPointerInfo().getWithOffset(2),
MVT::i16, ST->isVolatile(),
- CLI.setDebugLoc(dl).setChain(Chain)
- .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
- DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
- std::move(Args), 0);
+ CLI.setDebugLoc(dl).setChain(Chain).setCallee(
+ CallingConv::C, Type::getVoidTy(*DAG.getContext()),
+ DAG.getExternalSymbol("__misaligned_store",
+ getPointerTy(DAG.getDataLayout())),
+ std::move(Args), 0);
std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
return CallResult.second;
std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
return CallResult.second;
SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
LHS, RHS);
SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
LHS, RHS);
SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
Zero, Zero);
SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
Zero, Zero);
SDLoc dl(N);
SDValue LL, RL, AddendL, AddendH;
LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDLoc dl(N);
SDValue LL, RL, AddendL, AddendH;
LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
- Mul.getOperand(0), DAG.getConstant(0, MVT::i32));
+ Mul.getOperand(0), DAG.getConstant(0, dl, MVT::i32));
RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
- Mul.getOperand(1), DAG.getConstant(0, MVT::i32));
+ Mul.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
APInt HighMask = APInt::getHighBitsSet(64, 32);
unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
APInt HighMask = APInt::getHighBitsSet(64, 32);
unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
}
SDValue LH, RH;
LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
}
SDValue LH, RH;
LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
- Mul.getOperand(0), DAG.getConstant(1, MVT::i32));
+ Mul.getOperand(0), DAG.getConstant(1, dl, MVT::i32));
RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
- Mul.getOperand(1), DAG.getConstant(1, MVT::i32));
+ Mul.getOperand(1), DAG.getConstant(1, dl, MVT::i32));
SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
DAG.getVTList(MVT::i32, MVT::i32), AddendH,
AddendL, LL, RL);
SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
DAG.getVTList(MVT::i32, MVT::i32), AddendH,
AddendL, LL, RL);
// Extract components
SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
// Extract components
SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
LHSL, RHSL, Zero);
SDValue Carry(Lo.getNode(), 1);
SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
LHSL, RHSL, Zero);
SDValue Carry(Lo.getNode(), 1);
false, false, false, 0);
// Increment the pointer, VAList, to the next vararg
SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,
false, false, false, 0);
// Increment the pointer, VAList, to the next vararg
SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,
// Store the incremented VAList to the legalized pointer
InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,
MachinePointerInfo(SV), false, false, 0);
// Store the incremented VAList to the legalized pointer
InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,
MachinePointerInfo(SV), false, false, 0);
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
int FI = XFI->createLRSpillSlot(MF);
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
int FI = XFI->createLRSpillSlot(MF);
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
- return DAG.getLoad(getPointerTy(), SDLoc(Op), DAG.getEntryNode(), FIN,
- MachinePointerInfo::getFixedStack(FI), false, false,
- false, 0);
+ return DAG.getLoad(
+ getPointerTy(DAG.getDataLayout()), SDLoc(Op), DAG.getEntryNode(), FIN,
+ MachinePointerInfo::getFixedStack(FI), false, false, false, 0);
- OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),
- Addr, MachinePointerInfo(TrmpAddr), false, false,
- 0);
+ OutChains[0] = DAG.getStore(Chain, dl,
+ DAG.getConstant(0x0a3cd805, dl, MVT::i32), Addr,
+ MachinePointerInfo(TrmpAddr), false, false, 0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
- DAG.getConstant(4, MVT::i32));
- OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),
- Addr, MachinePointerInfo(TrmpAddr, 4), false,
- false, 0);
+ DAG.getConstant(4, dl, MVT::i32));
+ OutChains[1] = DAG.getStore(Chain, dl,
+ DAG.getConstant(0xd80456c0, dl, MVT::i32), Addr,
+ MachinePointerInfo(TrmpAddr, 4), false, false, 0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
- DAG.getConstant(8, MVT::i32));
- OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),
- Addr, MachinePointerInfo(TrmpAddr, 8), false,
- false, 0);
+ DAG.getConstant(8, dl, MVT::i32));
+ OutChains[2] = DAG.getStore(Chain, dl,
+ DAG.getConstant(0x27fb0a3c, dl, MVT::i32), Addr,
+ MachinePointerInfo(TrmpAddr, 8), false, false, 0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
MachinePointerInfo(TrmpAddr, 12), false, false,
0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
MachinePointerInfo(TrmpAddr, 12), false, false,
0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
MachinePointerInfo(TrmpAddr, 16), false, false,
0);
OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
MachinePointerInfo(TrmpAddr, 16), false, false,
0);
if (N->getMemoryVT() == MVT::i32) {
if (N->getAlignment() < 4)
report_fatal_error("atomic load must be aligned");
if (N->getMemoryVT() == MVT::i32) {
if (N->getAlignment() < 4)
report_fatal_error("atomic load must be aligned");
- return DAG.getLoad(getPointerTy(), SDLoc(Op), N->getChain(),
- N->getBasePtr(), N->getPointerInfo(),
- N->isVolatile(), N->isNonTemporal(),
- N->isInvariant(), N->getAlignment(),
- N->getAAInfo(), N->getRanges());
+ return DAG.getLoad(getPointerTy(DAG.getDataLayout()), SDLoc(Op),
+ N->getChain(), N->getBasePtr(), N->getPointerInfo(),
+ N->isVolatile(), N->isNonTemporal(), N->isInvariant(),
+ N->getAlignment(), N->getAAInfo(), N->getRanges());
int offset = ResultMemLocs[i].first;
unsigned index = ResultMemLocs[i].second;
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
int offset = ResultMemLocs[i].first;
unsigned index = ResultMemLocs[i].second;
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
- SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };
+ SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, dl, MVT::i32) };
SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);
InVals[index] = load;
MemOpChains.push_back(load.getValue(1));
SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);
InVals[index] = load;
MemOpChains.push_back(load.getValue(1));
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = RetCCInfo.getNextStackOffset();
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = RetCCInfo.getNextStackOffset();
- Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
- getPointerTy(), true), dl);
+ Chain = DAG.getCALLSEQ_START(Chain,
+ DAG.getConstant(NumBytes, dl, PtrVT, true), dl);
SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
SmallVector<SDValue, 12> MemOpChains;
SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
SmallVector<SDValue, 12> MemOpChains;
MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
Chain, Arg,
MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
Chain, Arg,
- Chain = DAG.getCALLSEQ_END(Chain,
- DAG.getConstant(NumBytes, getPointerTy(), true),
- DAG.getConstant(0, getPointerTy(), true),
- InFlag, dl);
+ Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
+ DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we
InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
InVals.push_back(FIN);
MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
InVals.push_back(FIN);
MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,
- DAG.getConstant(Size, MVT::i32),
- Align, false, false,
+ DAG.getConstant(Size, dl, MVT::i32),
+ Align, false, false, false,
SmallVector<SDValue, 4> RetOps(1, Chain);
// Return on XCore is always a "retsp 0"
SmallVector<SDValue, 4> RetOps(1, Chain);
// Return on XCore is always a "retsp 0"
SmallVector<SDValue, 4> MemOpChains;
// Handle return values that must be copied to memory.
SmallVector<SDValue, 4> MemOpChains;
// Handle return values that must be copied to memory.
// fold (ladd 0, 0, x) -> 0, x & 1
if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
// fold (ladd 0, 0, x) -> 0, x & 1
if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
SDValue Ops[] = { Result, Carry };
return DAG.getMergeValues(Ops, dl);
}
SDValue Ops[] = { Result, Carry };
return DAG.getMergeValues(Ops, dl);
}
VT.getSizeInBits() - 1);
DAG.computeKnownBits(N2, KnownZero, KnownOne);
if ((KnownZero & Mask) == Mask) {
VT.getSizeInBits() - 1);
DAG.computeKnownBits(N2, KnownZero, KnownOne);
if ((KnownZero & Mask) == Mask) {
SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
SDValue Ops[] = { Result, Carry };
return DAG.getMergeValues(Ops, dl);
SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
SDValue Ops[] = { Result, Carry };
return DAG.getMergeValues(Ops, dl);
if ((KnownZero & Mask) == Mask) {
SDValue Borrow = N2;
SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
if ((KnownZero & Mask) == Mask) {
SDValue Borrow = N2;
SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
SDValue Ops[] = { Result, Borrow };
return DAG.getMergeValues(Ops, dl);
}
SDValue Ops[] = { Result, Borrow };
return DAG.getMergeValues(Ops, dl);
}
VT.getSizeInBits() - 1);
DAG.computeKnownBits(N2, KnownZero, KnownOne);
if ((KnownZero & Mask) == Mask) {
VT.getSizeInBits() - 1);
DAG.computeKnownBits(N2, KnownZero, KnownOne);
if ((KnownZero & Mask) == Mask) {
SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
SDValue Ops[] = { Result, Borrow };
return DAG.getMergeValues(Ops, dl);
SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
SDValue Ops[] = { Result, Borrow };
return DAG.getMergeValues(Ops, dl);
DAG.MaskedValueIsZero(Addend0, HighMask) &&
DAG.MaskedValueIsZero(Addend1, HighMask)) {
SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
DAG.MaskedValueIsZero(Addend0, HighMask) &&
DAG.MaskedValueIsZero(Addend1, HighMask)) {
SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
Addend0L, Addend1L);
SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
Addend0L, Addend1L);
- if (StoreBits % 8) {
- break;
- }
- unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(
+ assert((StoreBits % 8) == 0 &&
+ "Store size in bits must be a multiple of 8");
+ unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(
ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
unsigned Alignment = ST->getAlignment();
if (Alignment >= ABIAlignment) {
ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
unsigned Alignment = ST->getAlignment();
if (Alignment >= ABIAlignment) {
LD->getAlignment() == Alignment &&
!LD->isVolatile() && !LD->isIndexed() &&
Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
LD->getAlignment() == Alignment &&
!LD->isVolatile() && !LD->isIndexed() &&
Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
LD->getBasePtr(),
return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
LD->getBasePtr(),
- DAG.getConstant(StoreBits/8, MVT::i32),
- Alignment, false, ST->getPointerInfo(),
+ DAG.getConstant(StoreBits/8, dl, MVT::i32),
+ Alignment, false, isTail, ST->getPointerInfo(),
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type.
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type.
-bool
-XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
- Type *Ty) const {
+bool XCoreTargetLowering::isLegalAddressingMode(const DataLayout &DL,
+ const AddrMode &AM, Type *Ty,
+ unsigned AS) const {
if (Ty->getTypeID() == Type::VoidTyID)
return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
if (Ty->getTypeID() == Type::VoidTyID)
return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
// XCore Inline Assembly Support
//===----------------------------------------------------------------------===//
// XCore Inline Assembly Support
//===----------------------------------------------------------------------===//
-std::pair<unsigned, const TargetRegisterClass*>
-XCoreTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const {
+std::pair<unsigned, const TargetRegisterClass *>
+XCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
+ StringRef Constraint,
+ MVT VT) const {
}
// Use the default implementation in TargetLowering to convert the register
// constraint into a member of a register class.
}
// Use the default implementation in TargetLowering to convert the register
// constraint into a member of a register class.