+ BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
+ return;
+ }
+
+ // Moving EFLAGS to / from another register requires a push and a pop.
+ if (SrcRC == &X86::CCRRegClass) {
+ assert(SrcReg == X86::EFLAGS);
+ if (DestRC == &X86::GR64RegClass) {
+ BuildMI(MBB, MI, get(X86::PUSHFQ));
+ BuildMI(MBB, MI, get(X86::POP64r), DestReg);
+ return;
+ } else if (DestRC == &X86::GR32RegClass) {
+ BuildMI(MBB, MI, get(X86::PUSHFD));
+ BuildMI(MBB, MI, get(X86::POP32r), DestReg);
+ return;
+ }
+ } else if (DestRC == &X86::CCRRegClass) {
+ assert(DestReg == X86::EFLAGS);
+ if (SrcRC == &X86::GR64RegClass) {
+ BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
+ BuildMI(MBB, MI, get(X86::POPFQ));
+ return;
+ } else if (SrcRC == &X86::GR32RegClass) {
+ BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
+ BuildMI(MBB, MI, get(X86::POPFD));
+ return;
+ }
+ }
+
+ // Moving from ST(0) turns into FpGET_ST0_32 etc.
+ if (SrcRC == &X86::RSTRegClass) {
+ // Copying from ST(0)/ST(1).
+ assert((SrcReg == X86::ST0 || SrcReg == X86::ST1) &&
+ "Can only copy from ST(0)/ST(1) right now");
+ bool isST0 = SrcReg == X86::ST0;
+ unsigned Opc;
+ if (DestRC == &X86::RFP32RegClass)
+ Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
+ else if (DestRC == &X86::RFP64RegClass)
+ Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
+ else {
+ assert(DestRC == &X86::RFP80RegClass);
+ Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
+ }
+ BuildMI(MBB, MI, get(Opc), DestReg);
+ return;