-def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
- "meeb\t{$dst, $src2}",
- [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr12:$src2)))]>;
-def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
- "mdb\t{$dst, $src2}",
- [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr12:$src2)))]>;
-
-def FMADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
- "maebr\t{$dst, $src3, $src2}",
- [(set FP32:$dst, (fadd (fmul FP32:$src2, FP32:$src3),
- FP32:$src1))]>;
-def FMADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2, FP32:$src3),
- "maeb\t{$dst, $src3, $src2}",
- [(set FP32:$dst, (fadd (fmul (load rriaddr12:$src2),
- FP32:$src3),
- FP32:$src1))]>;
-
-def FMADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
- "madbr\t{$dst, $src3, $src2}",
- [(set FP64:$dst, (fadd (fmul FP64:$src2, FP64:$src3),
- FP64:$src1))]>;
-def FMADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2, FP64:$src3),
- "madb\t{$dst, $src3, $src2}",
- [(set FP64:$dst, (fadd (fmul (load rriaddr12:$src2),
- FP64:$src3),
- FP64:$src1))]>;
-
-def FMSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
- "msebr\t{$dst, $src3, $src2}",
- [(set FP32:$dst, (fsub (fmul FP32:$src2, FP32:$src3),
- FP32:$src1))]>;
-def FMSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2, FP32:$src3),
- "mseb\t{$dst, $src3, $src2}",
- [(set FP32:$dst, (fsub (fmul (load rriaddr12:$src2),
- FP32:$src3),
- FP32:$src1))]>;
-
-def FMSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
- "msdbr\t{$dst, $src3, $src2}",
- [(set FP64:$dst, (fsub (fmul FP64:$src2, FP64:$src3),
- FP64:$src1))]>;
-def FMSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2, FP64:$src3),
- "msdb\t{$dst, $src3, $src2}",
- [(set FP64:$dst, (fsub (fmul (load rriaddr12:$src2),
- FP64:$src3),
- FP64:$src1))]>;
-
-def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
- "debr\t{$dst, $src2}",
- [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
-def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
- "ddbr\t{$dst, $src2}",
- [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
-
-def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
- "deb\t{$dst, $src2}",
- [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr12:$src2)))]>;
-def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
- "ddb\t{$dst, $src2}",
- [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr12:$src2)))]>;
-
-} // isTwoAddress = 1
-
-def FSQRT32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
- "sqebr\t{$dst, $src}",
- [(set FP32:$dst, (fsqrt FP32:$src))]>;
-def FSQRT64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
- "sqdbr\t{$dst, $src}",
- [(set FP64:$dst, (fsqrt FP64:$src))]>;
-
-def FSQRT32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
- "sqeb\t{$dst, $src}",
- [(set FP32:$dst, (fsqrt (load rriaddr12:$src)))]>;
-def FSQRT64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
- "sqdb\t{$dst, $src}",
- [(set FP64:$dst, (fsqrt (load rriaddr12:$src)))]>;
-
-def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
- "ledbr\t{$dst, $src}",
- [(set FP32:$dst, (fround FP64:$src))]>;
-
-def FEXT32r64 : Pseudo<(outs FP64:$dst), (ins FP32:$src),
- "ldebr\t{$dst, $src}",
- [(set FP64:$dst, (fextend FP32:$src))]>;
-def FEXT32m64 : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
- "ldeb\t{$dst, $src}",
- [(set FP64:$dst, (fextend (load rriaddr12:$src)))]>;
-
-let Defs = [PSW] in {
-def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src),
- "cefbr\t{$dst, $src}",
- [(set FP32:$dst, (sint_to_fp GR32:$src)),
- (implicit PSW)]>;
-def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
- "cegbr\t{$dst, $src}",
- [(set FP32:$dst, (sint_to_fp GR64:$src)),
- (implicit PSW)]>;
-
-def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
- "cdfbr\t{$dst, $src}",
- [(set FP64:$dst, (sint_to_fp GR32:$src)),
- (implicit PSW)]>;
-def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
- "cdgbr\t{$dst, $src}",
- [(set FP64:$dst, (sint_to_fp GR64:$src)),
- (implicit PSW)]>;
-
-def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src),
- "cfebr\t{$dst, 5, $src}",
- [(set GR32:$dst, (fp_to_sint FP32:$src)),
- (implicit PSW)]>;
-def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
- "cfdbr\t{$dst, 5, $src}",
- [(set GR32:$dst, (fp_to_sint FP64:$src)),
- (implicit PSW)]>;
-
-def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
- "cgebr\t{$dst, 5, $src}",
- [(set GR64:$dst, (fp_to_sint FP32:$src)),
- (implicit PSW)]>;
-def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
- "cgdbr\t{$dst, 5, $src}",
- [(set GR64:$dst, (fp_to_sint FP64:$src)),
- (implicit PSW)]>;
-} // Defs = [PSW]
-
-def FBCONVG64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
- "lgdr\t{$dst, $src}",
- [(set GR64:$dst, (bitconvert FP64:$src))]>;
-def FBCONVF64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
- "ldgr\t{$dst, $src}",
- [(set FP64:$dst, (bitconvert GR64:$src))]>;
+// Square root.
+def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>;
+def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>;
+def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
+
+def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
+def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
+
+// Round to an integer, with the second operand (modifier M3) specifying
+// the rounding mode. These forms always check for inexact conditions.
+def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>;
+def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>;
+def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
+
+// frint rounds according to the current mode (modifier 0) and detects
+// inexact conditions.
+def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>;
+def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>;
+def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
+
+let Predicates = [FeatureFPExtension] in {
+ // Extended forms of the FIxBR instructions. M4 can be set to 4
+ // to suppress detection of inexact conditions.
+ def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>;
+ def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>;
+ def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>;
+
+ // fnearbyint is like frint but does not detect inexact conditions.
+ def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>;
+ def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>;
+ def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>;
+
+ // floor is no longer allowed to raise an inexact condition,
+ // so restrict it to the cases where the condition can be suppressed.
+ // Mode 7 is round towards -inf.
+ def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>;
+ def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>;
+ def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>;
+
+ // Same idea for ceil, where mode 6 is round towards +inf.
+ def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>;
+ def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>;
+ def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>;
+
+ // Same idea for trunc, where mode 5 is round towards zero.
+ def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>;
+ def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>;
+ def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>;
+
+ // Same idea for round, where mode 1 is round towards nearest with
+ // ties away from zero.
+ def : Pat<(frnd FP32:$src), (FIEBRA 1, FP32:$src, 4)>;
+ def : Pat<(frnd FP64:$src), (FIDBRA 1, FP64:$src, 4)>;
+ def : Pat<(frnd FP128:$src), (FIXBRA 1, FP128:$src, 4)>;
+}