-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
const TargetRegisterClass *RC) const {
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == SP::IntRegsRegisterClass)
BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
const TargetRegisterClass *RC) const {
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == SP::IntRegsRegisterClass)
BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
- .addReg(SrcReg, false, false, true);
+ .addReg(SrcReg, false, false, isKill);
else if (RC == SP::FPRegsRegisterClass)
BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
else if (RC == SP::FPRegsRegisterClass)
BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
- .addReg(SrcReg, false, false, true);
+ .addReg(SrcReg, false, false, isKill);
else if (RC == SP::DFPRegsRegisterClass)
BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
else if (RC == SP::DFPRegsRegisterClass)
BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
- .addReg(SrcReg, false, false, true);
+ .addReg(SrcReg, false, false, isKill);
else
assert(0 && "Can't store this register to stack slot");
}
void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
else
assert(0 && "Can't store this register to stack slot");
}
void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
- MIB.addReg(SrcReg, false, false, true);
+ MIB.addReg(SrcReg, false, false, isKill);
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
unsigned Opc = 0;