-static SDValue buildRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr,
- uint32_t RsrcDword1, uint64_t RsrcDword2And3) {
-
- SDValue PtrLo = DAG->getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
- SDValue PtrHi = DAG->getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
- if (RsrcDword1)
- PtrHi = SDValue(DAG->getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
- DAG->getConstant(RsrcDword1, MVT::i32)), 0);
-
- SDValue DataLo = DAG->getTargetConstant(
- RsrcDword2And3 & APInt::getAllOnesValue(32).getZExtValue(), MVT::i32);
- SDValue DataHi = DAG->getTargetConstant(RsrcDword2And3 >> 32, MVT::i32);
-
- const SDValue Ops[] = { PtrLo, PtrHi, DataLo, DataHi };
- return SDValue(DAG->getMachineNode(AMDGPU::SI_BUFFER_RSRC, DL,
- MVT::v4i32, Ops), 0);
-}
-
-/// \brief Return a resource descriptor with the 'Add TID' bit enabled
-/// The TID (Thread ID) is multipled by the stride value (bits [61:48]
-/// of the resource descriptor) to create an offset, which is added to the
-/// resource ponter.
-static SDValue buildScratchRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
-
- uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
- 0xffffffff; // Size
-
- return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
-}
-