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[X86] Remove some llvm_unreachables after switches that already have an unreachable...
[oota-llvm.git]
/
lib
/
Target
/
NVPTX
/
NVPTXISelDAGToDAG.h
diff --git
a/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
b/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
index 3aa1c8f72f561c151fb37752b72aed14ad31e01b..fe20580c83a20b00b94e2a2b495e457ac2e5b816 100644
(file)
--- a/
lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/
lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@
-11,6
+11,9
@@
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
+#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELDAGTODAG_H
+#define LLVM_LIB_TARGET_NVPTX_NVPTXISELDAGTODAG_H
+
#include "NVPTX.h"
#include "NVPTXISelLowering.h"
#include "NVPTXRegisterInfo.h"
#include "NVPTX.h"
#include "NVPTXISelLowering.h"
#include "NVPTXRegisterInfo.h"
@@
-23,14
+26,7
@@
using namespace llvm;
namespace {
class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
namespace {
class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
-
- // If true, generate corresponding FPCONTRACT. This is
- // language dependent (i.e. CUDA and OpenCL works differently).
- bool doFMAF64;
- bool doFMAF32;
- bool doFMAF64AGG;
- bool doFMAF32AGG;
- bool allowFMA;
+ const NVPTXTargetMachine &TM;
// If true, generate mul.wide from sext and mul
bool doMulWide;
// If true, generate mul.wide from sext and mul
bool doMulWide;
@@
-38,6
+34,7
@@
class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
int getDivF32Level() const;
bool usePrecSqrtF32() const;
bool useF32FTZ() const;
int getDivF32Level() const;
bool usePrecSqrtF32() const;
bool useF32FTZ() const;
+ bool allowFMA() const;
public:
explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
public:
explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
@@
-47,11
+44,11
@@
public:
const char *getPassName() const override {
return "NVPTX DAG->DAG Pattern Instruction Selection";
}
const char *getPassName() const override {
return "NVPTX DAG->DAG Pattern Instruction Selection";
}
-
- const NVPTXSubtarget
&
Subtarget;
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ const NVPTXSubtarget
*
Subtarget;
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-
char ConstraintCode
,
+
unsigned ConstraintID
,
std::vector<SDValue> &OutOps) override;
private:
// Include the pieces autogenerated from the target description.
std::vector<SDValue> &OutOps) override;
private:
// Include the pieces autogenerated from the target description.
@@
-59,10
+56,11
@@
private:
SDNode *Select(SDNode *N) override;
SDNode *SelectIntrinsicNoChain(SDNode *N);
SDNode *Select(SDNode *N) override;
SDNode *SelectIntrinsicNoChain(SDNode *N);
+ SDNode *SelectIntrinsicChain(SDNode *N);
SDNode *SelectTexSurfHandle(SDNode *N);
SDNode *SelectLoad(SDNode *N);
SDNode *SelectLoadVector(SDNode *N);
SDNode *SelectTexSurfHandle(SDNode *N);
SDNode *SelectLoad(SDNode *N);
SDNode *SelectLoadVector(SDNode *N);
- SDNode *SelectLDGLDU
Vector
(SDNode *N);
+ SDNode *SelectLDGLDU(SDNode *N);
SDNode *SelectStore(SDNode *N);
SDNode *SelectStoreVector(SDNode *N);
SDNode *SelectLoadParam(SDNode *N);
SDNode *SelectStore(SDNode *N);
SDNode *SelectStoreVector(SDNode *N);
SDNode *SelectLoadParam(SDNode *N);
@@
-73,8
+71,8
@@
private:
SDNode *SelectSurfaceIntrinsic(SDNode *N);
SDNode *SelectBFE(SDNode *N);
SDNode *SelectSurfaceIntrinsic(SDNode *N);
SDNode *SelectBFE(SDNode *N);
- inline SDValue getI32Imm(unsigned Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i32);
+ inline SDValue getI32Imm(unsigned Imm
, SDLoc DL
) {
+ return CurDAG->getTargetConstant(Imm,
DL,
MVT::i32);
}
// Match direct address complex pattern.
}
// Match direct address complex pattern.
@@
-98,3
+96,5
@@
private:
};
}
};
}
+
+#endif