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[Mips] MipsTargetStreamer refactoring.
[oota-llvm.git]
/
lib
/
Target
/
Mips
/
MipsSchedule.td
diff --git
a/lib/Target/Mips/MipsSchedule.td
b/lib/Target/Mips/MipsSchedule.td
index bb7d5f1a8838d1eed749b7ba1cbff75684cef4ca..2779064c41491909853c7486289371f306386f46 100644
(file)
--- a/
lib/Target/Mips/MipsSchedule.td
+++ b/
lib/Target/Mips/MipsSchedule.td
@@
-1,29
+1,34
@@
-//===- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===//
+//===-
-
MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
-//===---------------------------------------------------------------------===//
+//===---------------------------------------------------------------------
-
===//
-//===---------------------------------------------------------------------===//
+//===---------------------------------------------------------------------
-
===//
// Functional units across Mips chips sets. Based on GCC/Mips backend files.
// Functional units across Mips chips sets. Based on GCC/Mips backend files.
-//===---------------------------------------------------------------------===//
+//===---------------------------------------------------------------------
-
===//
def ALU : FuncUnit;
def IMULDIV : FuncUnit;
def ALU : FuncUnit;
def IMULDIV : FuncUnit;
-//===---------------------------------------------------------------------===//
+//===---------------------------------------------------------------------
-
===//
// Instruction Itinerary classes used for Mips
// Instruction Itinerary classes used for Mips
-//===---------------------------------------------------------------------===//
+//===---------------------------------------------------------------------
-
===//
def IIAlu : InstrItinClass;
def IIAlu : InstrItinClass;
+def IIArith : InstrItinClass;
+def IILogic : InstrItinClass;
def IILoad : InstrItinClass;
def IIStore : InstrItinClass;
def IIXfer : InstrItinClass;
def IIBranch : InstrItinClass;
def IIHiLo : InstrItinClass;
def IIImul : InstrItinClass;
def IILoad : InstrItinClass;
def IIStore : InstrItinClass;
def IIXfer : InstrItinClass;
def IIBranch : InstrItinClass;
def IIHiLo : InstrItinClass;
def IIImul : InstrItinClass;
+def IIImult : InstrItinClass;
def IIIdiv : InstrItinClass;
def IIIdiv : InstrItinClass;
+def IIseb : InstrItinClass;
+def IIslt : InstrItinClass;
def IIFcvt : InstrItinClass;
def IIFmove : InstrItinClass;
def IIFcmp : InstrItinClass;
def IIFcvt : InstrItinClass;
def IIFmove : InstrItinClass;
def IIFcmp : InstrItinClass;
@@
-35,13
+40,18
@@
def IIFdivDouble : InstrItinClass;
def IIFsqrtSingle : InstrItinClass;
def IIFsqrtDouble : InstrItinClass;
def IIFrecipFsqrtStep : InstrItinClass;
def IIFsqrtSingle : InstrItinClass;
def IIFsqrtDouble : InstrItinClass;
def IIFrecipFsqrtStep : InstrItinClass;
+def IIFLoad : InstrItinClass;
+def IIFStore : InstrItinClass;
+def IIFmoveC1 : InstrItinClass;
def IIPseudo : InstrItinClass;
def IIPseudo : InstrItinClass;
-//===---------------------------------------------------------------------===//
+//===---------------------------------------------------------------------
-
===//
// Mips Generic instruction itineraries.
// Mips Generic instruction itineraries.
-//===---------------------------------------------------------------------===//
+//===---------------------------------------------------------------------
-
===//
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
+ InstrItinData<IIArith , [InstrStage<1, [ALU]>]>,
+ InstrItinData<IILogic , [InstrStage<1, [ALU]>]>,
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
InstrItinData<IIXfer , [InstrStage<2, [ALU]>]>,
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
InstrItinData<IIXfer , [InstrStage<2, [ALU]>]>,
@@
-59,5
+69,8
@@
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
InstrItinData<IIFdivDouble , [InstrStage<36, [ALU]>]>,
InstrItinData<IIFsqrtSingle , [InstrStage<54, [ALU]>]>,
InstrItinData<IIFsqrtDouble , [InstrStage<12, [ALU]>]>,
InstrItinData<IIFdivDouble , [InstrStage<36, [ALU]>]>,
InstrItinData<IIFsqrtSingle , [InstrStage<54, [ALU]>]>,
InstrItinData<IIFsqrtDouble , [InstrStage<12, [ALU]>]>,
- InstrItinData<IIFrecipFsqrtStep , [InstrStage<5, [ALU]>]>
+ InstrItinData<IIFrecipFsqrtStep , [InstrStage<5, [ALU]>]>,
+ InstrItinData<IIFLoad , [InstrStage<3, [ALU]>]>,
+ InstrItinData<IIFStore , [InstrStage<1, [ALU]>]>,
+ InstrItinData<IIFmoveC1 , [InstrStage<2, [ALU]>]>
]>;
]>;