-std::vector<bool> MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
- std::vector<bool> Allocatable(NumRegs);
- for (MRegisterInfo::regclass_iterator I = regclass_begin(),
- E = regclass_end(); I != E; ++I) {
- const TargetRegisterClass *RC = *I;
- for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
- E = RC->allocation_order_end(MF); I != E; ++I)
- Allocatable[*I] = true;
+/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
+/// register.
+const TargetRegisterClass *
+MRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT,
+ unsigned reg) const {
+ assert(isPhysicalRegister(reg) && "reg must be a physical register");
+ // Pick the register class of the right type that contains this physreg.
+ for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I)
+ if ((*I)->hasType(VT) && (*I)->contains(reg))
+ return *I;
+ assert(false && "Couldn't find the register class");
+ return 0;
+}
+
+
+/// getAllocatableSetForRC - Toggle the bits that represent allocatable
+/// registers for the specific register class.
+static void getAllocatableSetForRC(MachineFunction &MF,
+ const TargetRegisterClass *RC, BitVector &R){
+ for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
+ E = RC->allocation_order_end(MF); I != E; ++I)
+ R.set(*I);
+}
+
+BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF,
+ const TargetRegisterClass *RC) const {
+ BitVector Allocatable(NumRegs);
+ if (RC) {
+ getAllocatableSetForRC(MF, RC, Allocatable);
+ return Allocatable;