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[PowerPC] Enable interleaved-access vectorization
[oota-llvm.git]
/
lib
/
Target
/
BPF
/
BPFISelLowering.cpp
diff --git
a/lib/Target/BPF/BPFISelLowering.cpp
b/lib/Target/BPF/BPFISelLowering.cpp
index 543c79a9c6318c5e74a2f28f2b038c4cb68efcce..58498a1aec7d9eb284e5a46b08553cbc636fef79 100644
(file)
--- a/
lib/Target/BPF/BPFISelLowering.cpp
+++ b/
lib/Target/BPF/BPFISelLowering.cpp
@@
-63,11
+63,11
@@
public:
std::string Str;
raw_string_ostream OS(Str);
std::string Str;
raw_string_ostream OS(Str);
- if (DLoc
.isUnknown() == false
) {
-
DILocation DIL(DLoc.getAsMDNode(Fn.getContext())
);
- StringRef Filename = DIL
.
getFilename();
- unsigned Line = DIL
.getLineNumber
();
- unsigned Column = DIL
.getColumnNumber
();
+ if (DLoc) {
+
auto DIL = DLoc.get(
);
+ StringRef Filename = DIL
->
getFilename();
+ unsigned Line = DIL
->getLine
();
+ unsigned Column = DIL
->getColumn
();
OS << Filename << ':' << Line << ':' << Column << ' ';
}
OS << Filename << ':' << Line << ':' << Column << ' ';
}
@@
-88,14
+88,15
@@
public:
int DiagnosticInfoUnsupported::KindID = 0;
}
int DiagnosticInfoUnsupported::KindID = 0;
}
-BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM)
+BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
+ const BPFSubtarget &STI)
: TargetLowering(TM) {
// Set up the register classes.
addRegisterClass(MVT::i64, &BPF::GPRRegClass);
// Compute derived properties from the register classes
: TargetLowering(TM) {
// Set up the register classes.
addRegisterClass(MVT::i64, &BPF::GPRRegClass);
// Compute derived properties from the register classes
- computeRegisterProperties();
+ computeRegisterProperties(
STI.getRegisterInfo()
);
setStackPointerRegisterToSaveRestore(BPF::R11);
setStackPointerRegisterToSaveRestore(BPF::R11);
@@
-136,7
+137,6
@@
BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM)
setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
- setOperationAction(ISD::BSWAP, MVT::i64, Expand);
setOperationAction(ISD::CTTZ, MVT::i64, Custom);
setOperationAction(ISD::CTLZ, MVT::i64, Custom);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
setOperationAction(ISD::CTTZ, MVT::i64, Custom);
setOperationAction(ISD::CTLZ, MVT::i64, Custom);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
@@
-302,8
+302,9
@@
SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
DAG.getContext()->diagnose(Err);
}
DAG.getContext()->diagnose(Err);
}
+ auto PtrVT = getPointerTy(MF.getDataLayout());
Chain = DAG.getCALLSEQ_START(
Chain = DAG.getCALLSEQ_START(
- Chain, DAG.getConstant(NumBytes,
getPointerTy()
, true), CLI.DL);
+ Chain, DAG.getConstant(NumBytes,
CLI.DL, PtrVT
, true), CLI.DL);
SmallVector<std::pair<unsigned, SDValue>, 5> RegsToPass;
SmallVector<std::pair<unsigned, SDValue>, 5> RegsToPass;
@@
-350,10
+351,10
@@
SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
- Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL,
getPointerTy()
,
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL,
PtrVT
,
G->getOffset(), 0);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
G->getOffset(), 0);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
- Callee = DAG.getTargetExternalSymbol(E->getSymbol(),
getPointerTy()
, 0);
+ Callee = DAG.getTargetExternalSymbol(E->getSymbol(),
PtrVT
, 0);
// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
@@
-374,8
+375,8
@@
SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// Create the CALLSEQ_END node.
Chain = DAG.getCALLSEQ_END(
// Create the CALLSEQ_END node.
Chain = DAG.getCALLSEQ_END(
- Chain, DAG.getConstant(NumBytes,
getPointerTy()
, true),
- DAG.getConstant(0,
getPointerTy()
, true), InFlag, CLI.DL);
+ Chain, DAG.getConstant(NumBytes,
CLI.DL, PtrVT
, true),
+ DAG.getConstant(0,
CLI.DL, PtrVT
, true), InFlag, CLI.DL);
InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we
InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we
@@
-487,7
+488,7
@@
SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
NegateCC(LHS, RHS, CC);
return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
NegateCC(LHS, RHS, CC);
return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
- DAG.getConstant(CC, MVT::i64), Dest);
+ DAG.getConstant(CC,
DL,
MVT::i64), Dest);
}
SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
}
SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
@@
-500,7
+501,7
@@
SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
NegateCC(LHS, RHS, CC);
NegateCC(LHS, RHS, CC);
- SDValue TargetCC = DAG.getConstant(CC, MVT::i64);
+ SDValue TargetCC = DAG.getConstant(CC,
DL,
MVT::i64);
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
@@
-509,9
+510,9
@@
SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
}
const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
- switch (Opcode) {
-
default
:
-
return NULL
;
+ switch (
(BPFISD::NodeType)
Opcode) {
+
case BPFISD::FIRST_NUMBER
:
+
break
;
case BPFISD::RET_FLAG:
return "BPFISD::RET_FLAG";
case BPFISD::CALL:
case BPFISD::RET_FLAG:
return "BPFISD::RET_FLAG";
case BPFISD::CALL:
@@
-523,6
+524,7
@@
const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
case BPFISD::Wrapper:
return "BPFISD::Wrapper";
}
case BPFISD::Wrapper:
return "BPFISD::Wrapper";
}
+ return nullptr;
}
SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
}
SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
@@
-537,13
+539,10
@@
SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
MachineBasicBlock *
BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const {
MachineBasicBlock *
BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const {
- unsigned Opc = MI->getOpcode();
-
- const TargetInstrInfo &TII =
- *getTargetMachine().getSubtargetImpl()->getInstrInfo();
+ const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
DebugLoc DL = MI->getDebugLoc();
DebugLoc DL = MI->getDebugLoc();
- assert(
Opc
== BPF::Select && "Unexpected instr type to insert");
+ assert(
MI->getOpcode()
== BPF::Select && "Unexpected instr type to insert");
// To "insert" a SELECT instruction, we actually have to insert the diamond
// control-flow pattern. The incoming instruction knows the destination vreg
// To "insert" a SELECT instruction, we actually have to insert the diamond
// control-flow pattern. The incoming instruction knows the destination vreg