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[AVX512] Remove alternate data type versions of VALIGND, VALIGNQ, VMOVSHDUP and VMOVS...
[oota-llvm.git]
/
lib
/
Target
/
ARM
/
ARMSubtarget.h
diff --git
a/lib/Target/ARM/ARMSubtarget.h
b/lib/Target/ARM/ARMSubtarget.h
index dd1ab3aabcfb9f43645f5523e56c9b7ecab14af1..a8b28018f1b294edbc12ed500e9d5a8f6c4aa13a 100644
(file)
--- a/
lib/Target/ARM/ARMSubtarget.h
+++ b/
lib/Target/ARM/ARMSubtarget.h
@@
-43,11
+43,17
@@
class ARMSubtarget : public ARMGenSubtargetInfo {
protected:
enum ARMProcFamilyEnum {
Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
protected:
enum ARMProcFamilyEnum {
Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
- CortexA17, CortexR5, Swift, CortexA53, CortexA57, Krait,
+ CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexA35, CortexA53,
+ CortexA57, CortexA72, Krait, Swift
};
enum ARMProcClassEnum {
None, AClass, RClass, MClass
};
};
enum ARMProcClassEnum {
None, AClass, RClass, MClass
};
+ enum ARMArchEnum {
+ ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
+ ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
+ ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a
+ };
/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
ARMProcFamilyEnum ARMProcFamily;
/// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
ARMProcFamilyEnum ARMProcFamily;
@@
-55,17
+61,23
@@
protected:
/// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
ARMProcClassEnum ARMProcClass;
/// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
ARMProcClassEnum ARMProcClass;
+ /// ARMArch - ARM architecture
+ ARMArchEnum ARMArch;
+
/// HasV4TOps, HasV5TOps, HasV5TEOps,
/// HasV4TOps, HasV5TOps, HasV5TEOps,
- /// HasV6Ops, HasV6MOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
+ /// HasV6Ops, HasV6MOps, HasV6
KOps, HasV6
T2Ops, HasV7Ops, HasV8Ops -
/// Specify whether target support specific ARM ISA variants.
bool HasV4TOps;
bool HasV5TOps;
bool HasV5TEOps;
bool HasV6Ops;
bool HasV6MOps;
/// Specify whether target support specific ARM ISA variants.
bool HasV4TOps;
bool HasV5TOps;
bool HasV5TEOps;
bool HasV6Ops;
bool HasV6MOps;
+ bool HasV6KOps;
bool HasV6T2Ops;
bool HasV7Ops;
bool HasV8Ops;
bool HasV6T2Ops;
bool HasV7Ops;
bool HasV8Ops;
+ bool HasV8_1aOps;
+ bool HasV8_2aOps;
/// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
/// floating point ISAs are supported.
/// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
/// floating point ISAs are supported.
@@
-98,28
+110,33
@@
protected:
/// InThumbMode - True if compiling for Thumb, false for ARM.
bool InThumbMode;
/// InThumbMode - True if compiling for Thumb, false for ARM.
bool InThumbMode;
+ /// UseSoftFloat - True if we're using software floating point features.
+ bool UseSoftFloat;
+
/// HasThumb2 - True if Thumb2 instructions are supported.
bool HasThumb2;
/// NoARM - True if subtarget does not support ARM mode execution.
bool NoARM;
/// HasThumb2 - True if Thumb2 instructions are supported.
bool HasThumb2;
/// NoARM - True if subtarget does not support ARM mode execution.
bool NoARM;
- ///
IsR9Reserved - True if R9 is a not available as
general purpose register.
- bool
IsR9Reserved
;
+ ///
ReserveR9 - True if R9 is not available as a
general purpose register.
+ bool
ReserveR9
;
- ///
UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
- /// imms (including global addresses).
- bool
Use
Movt;
+ ///
NoMovt - True if MOVT / MOVW pairs are not used for materialization of
+ ///
32-bit
imms (including global addresses).
+ bool
No
Movt;
/// SupportsTailCall - True if the OS supports tail call. The dynamic linker
/// must be able to synthesize call stubs for interworking between ARM and
/// Thumb.
bool SupportsTailCall;
/// SupportsTailCall - True if the OS supports tail call. The dynamic linker
/// must be able to synthesize call stubs for interworking between ARM and
/// Thumb.
bool SupportsTailCall;
- /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
- /// only so far)
+ /// HasFP16 - True if subtarget supports half-precision FP conversions
bool HasFP16;
bool HasFP16;
+ /// HasFullFP16 - True if subtarget supports half-precision FP operations
+ bool HasFullFP16;
+
/// HasD16 - True if subtarget is limited to 16 double precision
/// FP registers for VFPv3.
bool HasD16;
/// HasD16 - True if subtarget is limited to 16 double precision
/// FP registers for VFPv3.
bool HasD16;
@@
-185,25
+202,31
@@
protected:
/// particularly effective at zeroing a VFP register.
bool HasZeroCycleZeroing;
/// particularly effective at zeroing a VFP register.
bool HasZeroCycleZeroing;
- ///
AllowsUnalignedMem - If true, the subtarget
allows unaligned memory
+ ///
StrictAlign - If true, the subtarget dis
allows unaligned memory
/// accesses for some types. For details, see
/// ARMTargetLowering::allowsMisalignedMemoryAccesses().
/// accesses for some types. For details, see
/// ARMTargetLowering::allowsMisalignedMemoryAccesses().
- bool
AllowsUnalignedMem
;
+ bool
StrictAlign
;
/// RestrictIT - If true, the subtarget disallows generation of deprecated IT
/// blocks to conform to ARMv8 rule.
bool RestrictIT;
/// RestrictIT - If true, the subtarget disallows generation of deprecated IT
/// blocks to conform to ARMv8 rule.
bool RestrictIT;
- ///
Thumb2DSP - If true, the subtarget supports the v7
DSP (saturating arith
- /// and such) instructions
in Thumb2 code
.
- bool
Thumb2
DSP;
+ ///
HasDSP - If true, the subtarget supports the
DSP (saturating arith
+ /// and such) instructions.
+ bool
Has
DSP;
/// NaCl TRAP instruction is generated instead of the regular TRAP.
bool UseNaClTrap;
/// NaCl TRAP instruction is generated instead of the regular TRAP.
bool UseNaClTrap;
+ /// Generate calls via indirect call instructions.
+ bool GenLongCalls;
+
/// Target machine allowed unsafe FP math (such as use of NEON fp)
bool UnsafeFPMath;
/// Target machine allowed unsafe FP math (such as use of NEON fp)
bool UnsafeFPMath;
+ /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
+ bool UseSjLjEH;
+
/// stackAlignment - The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
unsigned stackAlignment;
/// stackAlignment - The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
unsigned stackAlignment;
@@
-232,8
+255,8
@@
public:
/// This constructor initializes the data members to match that
/// of the specified triple.
///
/// This constructor initializes the data members to match that
/// of the specified triple.
///
- ARMSubtarget(const
std::string &TT, const std::string &CPU
,
- const
std::string &FS, const
ARMBaseTargetMachine &TM, bool IsLittle);
+ ARMSubtarget(const
Triple &TT, const std::string &CPU, const std::string &FS
,
+ const ARMBaseTargetMachine &TM, bool IsLittle);
/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
/// that still makes it profitable to inline the call.
/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
/// that still makes it profitable to inline the call.
@@
-284,9
+307,12
@@
public:
bool hasV5TEOps() const { return HasV5TEOps; }
bool hasV6Ops() const { return HasV6Ops; }
bool hasV6MOps() const { return HasV6MOps; }
bool hasV5TEOps() const { return HasV5TEOps; }
bool hasV6Ops() const { return HasV6Ops; }
bool hasV6MOps() const { return HasV6MOps; }
+ bool hasV6KOps() const { return HasV6KOps; }
bool hasV6T2Ops() const { return HasV6T2Ops; }
bool hasV7Ops() const { return HasV7Ops; }
bool hasV8Ops() const { return HasV8Ops; }
bool hasV6T2Ops() const { return HasV6T2Ops; }
bool hasV7Ops() const { return HasV7Ops; }
bool hasV8Ops() const { return HasV8Ops; }
+ bool hasV8_1aOps() const { return HasV8_1aOps; }
+ bool hasV8_2aOps() const { return HasV8_2aOps; }
bool isCortexA5() const { return ARMProcFamily == CortexA5; }
bool isCortexA7() const { return ARMProcFamily == CortexA7; }
bool isCortexA5() const { return ARMProcFamily == CortexA5; }
bool isCortexA7() const { return ARMProcFamily == CortexA7; }
@@
-310,7
+336,8
@@
public:
bool hasCRC() const { return HasCRC; }
bool hasVirtualization() const { return HasVirtualization; }
bool useNEONForSinglePrecisionFP() const {
bool hasCRC() const { return HasCRC; }
bool hasVirtualization() const { return HasVirtualization; }
bool useNEONForSinglePrecisionFP() const {
- return hasNEON() && UseNEONForSinglePrecisionFP; }
+ return hasNEON() && UseNEONForSinglePrecisionFP;
+ }
bool hasDivide() const { return HasHardwareDivide; }
bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
bool hasDivide() const { return HasHardwareDivide; }
bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
@@
-332,16
+359,20
@@
public:
bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
bool hasRAS() const { return HasRAS; }
bool hasMPExtension() const { return HasMPExtension; }
bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
bool hasRAS() const { return HasRAS; }
bool hasMPExtension() const { return HasMPExtension; }
- bool has
Thumb2DSP() const { return Thumb2
DSP; }
+ bool has
DSP() const { return Has
DSP; }
bool useNaClTrap() const { return UseNaClTrap; }
bool useNaClTrap() const { return UseNaClTrap; }
+ bool useSjLjEH() const { return UseSjLjEH; }
+ bool genLongCalls() const { return GenLongCalls; }
bool hasFP16() const { return HasFP16; }
bool hasD16() const { return HasD16; }
bool hasFP16() const { return HasFP16; }
bool hasD16() const { return HasD16; }
+ bool hasFullFP16() const { return HasFullFP16; }
const Triple &getTargetTriple() const { return TargetTriple; }
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
bool isTargetIOS() const { return TargetTriple.isiOS(); }
const Triple &getTargetTriple() const { return TargetTriple; }
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
bool isTargetIOS() const { return TargetTriple.isiOS(); }
+ bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
@@
-363,6
+394,11
@@
public:
TargetTriple.getEnvironment() == Triple::EABIHF) &&
!isTargetDarwin() && !isTargetWindows();
}
TargetTriple.getEnvironment() == Triple::EABIHF) &&
!isTargetDarwin() && !isTargetWindows();
}
+ bool isTargetGNUAEABI() const {
+ return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
+ TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
+ !isTargetDarwin() && !isTargetWindows();
+ }
// ARM Targets that support EHABI exception handling standard
// Darwin uses SjLj. Other targets might need more checks.
// ARM Targets that support EHABI exception handling standard
// Darwin uses SjLj. Other targets might need more checks.
@@
-371,7
+407,7
@@
public:
TargetTriple.getEnvironment() == Triple::GNUEABI ||
TargetTriple.getEnvironment() == Triple::EABIHF ||
TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
TargetTriple.getEnvironment() == Triple::GNUEABI ||
TargetTriple.getEnvironment() == Triple::EABIHF ||
TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
-
TargetTriple.getEnvironment() == Triple::Android
) &&
+
isTargetAndroid()
) &&
!isTargetDarwin() && !isTargetWindows();
}
!isTargetDarwin() && !isTargetWindows();
}
@@
-379,15
+415,15
@@
public:
// FIXME: this is invalid for WindowsCE
return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
TargetTriple.getEnvironment() == Triple::EABIHF ||
// FIXME: this is invalid for WindowsCE
return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
TargetTriple.getEnvironment() == Triple::EABIHF ||
- isTargetWindows();
- }
- bool isTargetAndroid() const {
- return TargetTriple.getEnvironment() == Triple::Android;
+ isTargetWindows() || isAAPCS16_ABI();
}
}
+ bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
bool isAPCS_ABI() const;
bool isAAPCS_ABI() const;
bool isAPCS_ABI() const;
bool isAAPCS_ABI() const;
+ bool isAAPCS16_ABI() const;
+ bool useSoftFloat() const { return UseSoftFloat; }
bool isThumb() const { return InThumbMode; }
bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
bool isThumb2() const { return InThumbMode && HasThumb2; }
bool isThumb() const { return InThumbMode; }
bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
bool isThumb2() const { return InThumbMode && HasThumb2; }
@@
-396,17
+432,17
@@
public:
bool isRClass() const { return ARMProcClass == RClass; }
bool isAClass() const { return ARMProcClass == AClass; }
bool isRClass() const { return ARMProcClass == RClass; }
bool isAClass() const { return ARMProcClass == AClass; }
- bool is
V6M
() const {
- return isT
humb1Only() && isMClass()
;
+ bool is
R9Reserved
() const {
+ return isT
argetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9
;
}
}
- bool
isR9Reserved() const { return IsR9Reserved; }
+ bool
useStride4VFPs(const MachineFunction &MF) const;
bool useMovt(const MachineFunction &MF) const;
bool supportsTailCall() const { return SupportsTailCall; }
bool useMovt(const MachineFunction &MF) const;
bool supportsTailCall() const { return SupportsTailCall; }
- bool allowsUnalignedMem() const { return
AllowsUnalignedMem
; }
+ bool allowsUnalignedMem() const { return
!StrictAlign
; }
bool restrictIT() const { return RestrictIT; }
bool restrictIT() const { return RestrictIT; }
@@
-420,8
+456,11
@@
public:
/// compiler runtime or math libraries.
bool hasSinCos() const;
/// compiler runtime or math libraries.
bool hasSinCos() const;
+ /// Returns true if machine scheduler should be enabled.
+ bool enableMachineScheduler() const override;
+
/// True for some subtargets at > -O0.
/// True for some subtargets at > -O0.
- bool enablePost
Machine
Scheduler() const override;
+ bool enablePost
RA
Scheduler() const override;
// enableAtomicExpand- True if we need to expand our atomics.
bool enableAtomicExpand() const override;
// enableAtomicExpand- True if we need to expand our atomics.
bool enableAtomicExpand() const override;
@@
-441,6
+480,8
@@
public:
/// symbol.
bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
/// symbol.
bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
+ /// True if fast-isel is used.
+ bool useFastISel() const;
};
} // End llvm namespace
};
} // End llvm namespace