+ "vld1", Dt, "${dst:dregpair}, $addr", "",
+ [(set QPR:$dst, (Ty (int_arm_neon_vld1 addrmode6:$addr)))]>;
+
+def VLD1d8 : VLD1D<0b0000, "8", v8i8>;
+def VLD1d16 : VLD1D<0b0100, "16", v4i16>;
+def VLD1d32 : VLD1D<0b1000, "32", v2i32>;
+def VLD1df : VLD1D<0b1000, "32", v2f32>;
+def VLD1d64 : VLD1D<0b1100, "64", v1i64>;
+
+def VLD1q8 : VLD1Q<0b0000, "8", v16i8>;
+def VLD1q16 : VLD1Q<0b0100, "16", v8i16>;
+def VLD1q32 : VLD1Q<0b1000, "32", v4i32>;
+def VLD1qf : VLD1Q<0b1000, "32", v4f32>;
+def VLD1q64 : VLD1Q<0b1100, "64", v2i64>;
+
+let mayLoad = 1 in {
+
+// ...with address register writeback:
+class VLD1DWB<bits<4> op7_4, string Dt>
+ : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb),
+ (ins addrmode6:$addr), IIC_VLD1,
+ "vld1", Dt, "\\{$dst\\}, $addr",
+ "$addr.addr = $wb", []>;
+class VLD1QWB<bits<4> op7_4, string Dt>
+ : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb),
+ (ins addrmode6:$addr), IIC_VLD1,
+ "vld1", Dt, "${dst:dregpair}, $addr",
+ "$addr.addr = $wb", []>;