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MC: Modernize MCOperand API naming. NFC.
[oota-llvm.git]
/
lib
/
Target
/
AArch64
/
Disassembler
/
AArch64Disassembler.cpp
diff --git
a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 1c8c0a665cc13d7c7d2d878ce7ec03d9ec6d8927..a1ed703d1bf43608dd5df64d048d79c3f1e5ab6a 100644
(file)
--- a/
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@
-261,7
+261,7
@@
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
return Fail;
unsigned Register = FPR128DecoderTable[RegNo];
return Fail;
unsigned Register = FPR128DecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-290,7
+290,7
@@
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
return Fail;
unsigned Register = FPR64DecoderTable[RegNo];
return Fail;
unsigned Register = FPR64DecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-311,7
+311,7
@@
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
return Fail;
unsigned Register = FPR32DecoderTable[RegNo];
return Fail;
unsigned Register = FPR32DecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-332,7
+332,7
@@
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
return Fail;
unsigned Register = FPR16DecoderTable[RegNo];
return Fail;
unsigned Register = FPR16DecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-353,7
+353,7
@@
static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
return Fail;
unsigned Register = FPR8DecoderTable[RegNo];
return Fail;
unsigned Register = FPR8DecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-374,7
+374,7
@@
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
return Fail;
unsigned Register = GPR64DecoderTable[RegNo];
return Fail;
unsigned Register = GPR64DecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-386,7
+386,7
@@
static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
unsigned Register = GPR64DecoderTable[RegNo];
if (Register == AArch64::XZR)
Register = AArch64::SP;
unsigned Register = GPR64DecoderTable[RegNo];
if (Register == AArch64::XZR)
Register = AArch64::SP;
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-407,7
+407,7
@@
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
return Fail;
unsigned Register = GPR32DecoderTable[RegNo];
return Fail;
unsigned Register = GPR32DecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-420,7
+420,7
@@
static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
unsigned Register = GPR32DecoderTable[RegNo];
if (Register == AArch64::WZR)
Register = AArch64::WSP;
unsigned Register = GPR32DecoderTable[RegNo];
if (Register == AArch64::WZR)
Register = AArch64::WSP;
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-441,7
+441,7
@@
static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
return Fail;
unsigned Register = VectorDecoderTable[RegNo];
return Fail;
unsigned Register = VectorDecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-461,7
+461,7
@@
static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
if (RegNo > 31)
return Fail;
unsigned Register = QQDecoderTable[RegNo];
if (RegNo > 31)
return Fail;
unsigned Register = QQDecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-484,7
+484,7
@@
static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
if (RegNo > 31)
return Fail;
unsigned Register = QQQDecoderTable[RegNo];
if (RegNo > 31)
return Fail;
unsigned Register = QQQDecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-508,7
+508,7
@@
static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
if (RegNo > 31)
return Fail;
unsigned Register = QQQQDecoderTable[RegNo];
if (RegNo > 31)
return Fail;
unsigned Register = QQQQDecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-528,7
+528,7
@@
static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
if (RegNo > 31)
return Fail;
unsigned Register = DDDecoderTable[RegNo];
if (RegNo > 31)
return Fail;
unsigned Register = DDDecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-551,7
+551,7
@@
static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
if (RegNo > 31)
return Fail;
unsigned Register = DDDDecoderTable[RegNo];
if (RegNo > 31)
return Fail;
unsigned Register = DDDDecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-575,7
+575,7
@@
static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
if (RegNo > 31)
return Fail;
unsigned Register = DDDDDecoderTable[RegNo];
if (RegNo > 31)
return Fail;
unsigned Register = DDDDDecoderTable[RegNo];
- Inst.addOperand(MCOperand::
C
reateReg(Register));
+ Inst.addOperand(MCOperand::
c
reateReg(Register));
return Success;
}
return Success;
}
@@
-584,14
+584,14
@@
static DecodeStatus DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm,
const void *Decoder) {
// scale{5} is asserted as 1 in tblgen.
Imm |= 0x20;
const void *Decoder) {
// scale{5} is asserted as 1 in tblgen.
Imm |= 0x20;
- Inst.addOperand(MCOperand::
C
reateImm(64 - Imm));
+ Inst.addOperand(MCOperand::
c
reateImm(64 - Imm));
return Success;
}
static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
uint64_t Addr,
const void *Decoder) {
return Success;
}
static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
uint64_t Addr,
const void *Decoder) {
- Inst.addOperand(MCOperand::
C
reateImm(64 - Imm));
+ Inst.addOperand(MCOperand::
c
reateImm(64 - Imm));
return Success;
}
return Success;
}
@@
-607,21
+607,21
@@
static DecodeStatus DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm,
if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Inst.getOpcode() != AArch64::LDRXl, 0, 4))
if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Inst.getOpcode() != AArch64::LDRXl, 0, 4))
- Inst.addOperand(MCOperand::
C
reateImm(ImmVal));
+ Inst.addOperand(MCOperand::
c
reateImm(ImmVal));
return Success;
}
static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address, const void *Decoder) {
return Success;
}
static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address, const void *Decoder) {
- Inst.addOperand(MCOperand::
C
reateImm((Imm >> 1) & 1));
- Inst.addOperand(MCOperand::
C
reateImm(Imm & 1));
+ Inst.addOperand(MCOperand::
c
reateImm((Imm >> 1) & 1));
+ Inst.addOperand(MCOperand::
c
reateImm(Imm & 1));
return Success;
}
static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder) {
return Success;
}
static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::
C
reateImm(Imm));
+ Inst.addOperand(MCOperand::
c
reateImm(Imm));
// Every system register in the encoding space is valid with the syntax
// S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
// Every system register in the encoding space is valid with the syntax
// S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
@@
-631,7
+631,7
@@
static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder) {
static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
uint64_t Address,
const void *Decoder) {
- Inst.addOperand(MCOperand::
C
reateImm(Imm));
+ Inst.addOperand(MCOperand::
c
reateImm(Imm));
return Success;
}
return Success;
}
@@
-654,20
+654,20
@@
static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
}
// Add the lane
}
// Add the lane
- Inst.addOperand(MCOperand::
C
reateImm(1));
+ Inst.addOperand(MCOperand::
c
reateImm(1));
return Success;
}
static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
unsigned Add) {
return Success;
}
static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
unsigned Add) {
- Inst.addOperand(MCOperand::
C
reateImm(Add - Imm));
+ Inst.addOperand(MCOperand::
c
reateImm(Add - Imm));
return Success;
}
static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
unsigned Add) {
return Success;
}
static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
unsigned Add) {
- Inst.addOperand(MCOperand::
C
reateImm((Imm + Add) & (Add - 1)));
+ Inst.addOperand(MCOperand::
c
reateImm((Imm + Add) & (Add - 1)));
return Success;
}
return Success;
}
@@
-787,7
+787,7
@@
static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
break;
}
break;
}
- Inst.addOperand(MCOperand::
C
reateImm(shift));
+ Inst.addOperand(MCOperand::
c
reateImm(shift));
return Success;
}
return Success;
}
@@
-819,8
+819,8
@@
static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
Inst.getOpcode() == AArch64::MOVKXi)
Inst.addOperand(Inst.getOperand(0));
Inst.getOpcode() == AArch64::MOVKXi)
Inst.addOperand(Inst.getOperand(0));
- Inst.addOperand(MCOperand::
C
reateImm(imm));
- Inst.addOperand(MCOperand::
C
reateImm(shift));
+ Inst.addOperand(MCOperand::
c
reateImm(imm));
+ Inst.addOperand(MCOperand::
c
reateImm(shift));
return Success;
}
return Success;
}
@@
-838,7
+838,7
@@
static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
return Fail;
case AArch64::PRFMui:
// Rt is an immediate in prefetch.
return Fail;
case AArch64::PRFMui:
// Rt is an immediate in prefetch.
- Inst.addOperand(MCOperand::
C
reateImm(Rt));
+ Inst.addOperand(MCOperand::
c
reateImm(Rt));
break;
case AArch64::STRBBui:
case AArch64::LDRBBui:
break;
case AArch64::STRBBui:
case AArch64::LDRBBui:
@@
-881,7
+881,7
@@
static DecodeStatus DecodeUnsignedLdStInstruction(llvm::MCInst &Inst,
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
- Inst.addOperand(MCOperand::
C
reateImm(offset));
+ Inst.addOperand(MCOperand::
c
reateImm(offset));
return Success;
}
return Success;
}
@@
-956,7
+956,7
@@
static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
return Fail;
case AArch64::PRFUMi:
// Rt is an immediate in prefetch.
return Fail;
case AArch64::PRFUMi:
// Rt is an immediate in prefetch.
- Inst.addOperand(MCOperand::
C
reateImm(Rt));
+ Inst.addOperand(MCOperand::
c
reateImm(Rt));
break;
case AArch64::STURBBi:
case AArch64::LDURBBi:
break;
case AArch64::STURBBi:
case AArch64::LDURBBi:
@@
-1057,7
+1057,7
@@
static DecodeStatus DecodeSignedLdStInstruction(llvm::MCInst &Inst,
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- Inst.addOperand(MCOperand::
C
reateImm(offset));
+ Inst.addOperand(MCOperand::
c
reateImm(offset));
bool IsLoad = fieldFromInstruction(insn, 22, 1);
bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
bool IsLoad = fieldFromInstruction(insn, 22, 1);
bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
@@
-1268,7
+1268,7
@@
static DecodeStatus DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn,
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
- Inst.addOperand(MCOperand::
C
reateImm(offset));
+ Inst.addOperand(MCOperand::
c
reateImm(offset));
// You shouldn't load to the same register twice in an instruction...
if (IsLoad && Rt == Rt2)
// You shouldn't load to the same register twice in an instruction...
if (IsLoad && Rt == Rt2)
@@
-1335,7
+1335,7
@@
static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
break;
}
break;
}
- Inst.addOperand(MCOperand::
C
reateImm(extend));
+ Inst.addOperand(MCOperand::
c
reateImm(extend));
return Success;
}
return Success;
}
@@
-1366,7
+1366,7
@@
static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst,
if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
return Fail;
}
if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
return Fail;
}
- Inst.addOperand(MCOperand::
C
reateImm(imm));
+ Inst.addOperand(MCOperand::
c
reateImm(imm));
return Success;
}
return Success;
}
@@
-1383,7
+1383,7
@@
static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
else
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
else
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
- Inst.addOperand(MCOperand::
C
reateImm(imm));
+ Inst.addOperand(MCOperand::
c
reateImm(imm));
switch (Inst.getOpcode()) {
default:
switch (Inst.getOpcode()) {
default:
@@
-1396,13
+1396,13
@@
static DecodeStatus DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn,
case AArch64::MOVIv4i32:
case AArch64::MVNIv2i32:
case AArch64::MVNIv4i32:
case AArch64::MOVIv4i32:
case AArch64::MVNIv2i32:
case AArch64::MVNIv4i32:
- Inst.addOperand(MCOperand::
C
reateImm((cmode & 6) << 2));
+ Inst.addOperand(MCOperand::
c
reateImm((cmode & 6) << 2));
break;
case AArch64::MOVIv2s_msl:
case AArch64::MOVIv4s_msl:
case AArch64::MVNIv2s_msl:
case AArch64::MVNIv4s_msl:
break;
case AArch64::MOVIv2s_msl:
case AArch64::MOVIv4s_msl:
case AArch64::MVNIv2s_msl:
case AArch64::MVNIv4s_msl:
- Inst.addOperand(MCOperand::
C
reateImm(cmode & 1 ? 0x110 : 0x108));
+ Inst.addOperand(MCOperand::
c
reateImm(cmode & 1 ? 0x110 : 0x108));
break;
}
break;
}
@@
-1421,8
+1421,8
@@
static DecodeStatus DecodeModImmTiedInstruction(llvm::MCInst &Inst,
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
- Inst.addOperand(MCOperand::
C
reateImm(imm));
- Inst.addOperand(MCOperand::
C
reateImm((cmode & 6) << 2));
+ Inst.addOperand(MCOperand::
c
reateImm(imm));
+ Inst.addOperand(MCOperand::
c
reateImm((cmode & 6) << 2));
return Success;
}
return Success;
}
@@
-1441,7
+1441,7
@@
static DecodeStatus DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn,
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
- Inst.addOperand(MCOperand::
C
reateImm(imm));
+ Inst.addOperand(MCOperand::
c
reateImm(imm));
return Success;
}
return Success;
}
@@
-1477,8
+1477,8
@@
static DecodeStatus DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn,
}
if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
}
if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
- Inst.addOperand(MCOperand::
C
reateImm(ImmVal));
- Inst.addOperand(MCOperand::
C
reateImm(12 * ShifterVal));
+ Inst.addOperand(MCOperand::
c
reateImm(ImmVal));
+ Inst.addOperand(MCOperand::
c
reateImm(12 * ShifterVal));
return Success;
}
return Success;
}
@@
-1494,7
+1494,7
@@
static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn,
imm |= ~((1LL << 26) - 1);
if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
imm |= ~((1LL << 26) - 1);
if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
- Inst.addOperand(MCOperand::
C
reateImm(imm));
+ Inst.addOperand(MCOperand::
c
reateImm(imm));
return Success;
}
return Success;
}
@@
-1508,8
+1508,8
@@
static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
uint64_t pstate_field = (op1 << 3) | op2;
uint64_t pstate_field = (op1 << 3) | op2;
- Inst.addOperand(MCOperand::
C
reateImm(pstate_field));
- Inst.addOperand(MCOperand::
C
reateImm(crm));
+ Inst.addOperand(MCOperand::
c
reateImm(pstate_field));
+ Inst.addOperand(MCOperand::
c
reateImm(crm));
bool ValidNamed;
const AArch64Disassembler *Dis =
bool ValidNamed;
const AArch64Disassembler *Dis =
@@
-1537,9
+1537,9
@@
static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
else
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
else
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
- Inst.addOperand(MCOperand::
C
reateImm(bit));
+ Inst.addOperand(MCOperand::
c
reateImm(bit));
if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
- Inst.addOperand(MCOperand::
C
reateImm(dst));
+ Inst.addOperand(MCOperand::
c
reateImm(dst));
return Success;
}
return Success;
}