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PR14492: Debug Info: Support for values of non-integer non-type template parameters.
[oota-llvm.git]
/
lib
/
CodeGen
/
SelectionDAG
/
ResourcePriorityQueue.cpp
diff --git
a/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
b/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
index c3794d5f7863dd6a888a993856ae5fa630da8785..473e1384e399b3a990512866f42a370d4fc3bf7e 100644
(file)
--- a/
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
+++ b/
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
@@
-21,13
+21,13
@@
#define DEBUG_TYPE "scheduler"
#include "llvm/CodeGen/ResourcePriorityQueue.h"
#define DEBUG_TYPE "scheduler"
#include "llvm/CodeGen/ResourcePriorityQueue.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/SelectionDAGNodes.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetMachine.h"
using namespace llvm;
using namespace llvm;
@@
-94,9
+94,9
@@
ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) {
continue;
for (unsigned i = 0, e = ScegN->getNumValues(); i != e; ++i) {
continue;
for (unsigned i = 0, e = ScegN->getNumValues(); i != e; ++i) {
-
EVT VT = ScegN->get
ValueType(i);
+
MVT VT = ScegN->getSimple
ValueType(i);
if (TLI->isTypeLegal(VT)
if (TLI->isTypeLegal(VT)
- && (TLI->getRegClassFor(VT)->getID() == RCId)) {
+
&& (TLI->getRegClassFor(VT)->getID() == RCId)) {
NumberDeps++;
break;
}
NumberDeps++;
break;
}
@@
-132,9
+132,9
@@
unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU,
for (unsigned i = 0, e = ScegN->getNumOperands(); i != e; ++i) {
const SDValue &Op = ScegN->getOperand(i);
for (unsigned i = 0, e = ScegN->getNumOperands(); i != e; ++i) {
const SDValue &Op = ScegN->getOperand(i);
-
EVT VT = Op.getNode()->get
ValueType(Op.getResNo());
+
MVT VT = Op.getNode()->getSimple
ValueType(Op.getResNo());
if (TLI->isTypeLegal(VT)
if (TLI->isTypeLegal(VT)
- && (TLI->getRegClassFor(VT)->getID() == RCId)) {
+
&& (TLI->getRegClassFor(VT)->getID() == RCId)) {
NumberDeps++;
break;
}
NumberDeps++;
break;
}
@@
-332,7
+332,7
@@
signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {
// Gen estimate.
for (unsigned i = 0, e = SU->getNode()->getNumValues(); i != e; ++i) {
// Gen estimate.
for (unsigned i = 0, e = SU->getNode()->getNumValues(); i != e; ++i) {
-
EVT VT = SU->getNode()->get
ValueType(i);
+
MVT VT = SU->getNode()->getSimple
ValueType(i);
if (TLI->isTypeLegal(VT)
&& TLI->getRegClassFor(VT)
&& TLI->getRegClassFor(VT)->getID() == RCId)
if (TLI->isTypeLegal(VT)
&& TLI->getRegClassFor(VT)
&& TLI->getRegClassFor(VT)->getID() == RCId)
@@
-341,7
+341,7
@@
signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {
// Kill estimate.
for (unsigned i = 0, e = SU->getNode()->getNumOperands(); i != e; ++i) {
const SDValue &Op = SU->getNode()->getOperand(i);
// Kill estimate.
for (unsigned i = 0, e = SU->getNode()->getNumOperands(); i != e; ++i) {
const SDValue &Op = SU->getNode()->getOperand(i);
-
EVT VT = Op.getNode()->get
ValueType(Op.getResNo());
+
MVT VT = Op.getNode()->getSimple
ValueType(Op.getResNo());
if (isa<ConstantSDNode>(Op.getNode()))
continue;
if (isa<ConstantSDNode>(Op.getNode()))
continue;
@@
-485,7
+485,7
@@
void ResourcePriorityQueue::scheduledNode(SUnit *SU) {
if (ScegN->isMachineOpcode()) {
// Estimate generated regs.
for (unsigned i = 0, e = ScegN->getNumValues(); i != e; ++i) {
if (ScegN->isMachineOpcode()) {
// Estimate generated regs.
for (unsigned i = 0, e = ScegN->getNumValues(); i != e; ++i) {
-
EVT VT = ScegN->get
ValueType(i);
+
MVT VT = ScegN->getSimple
ValueType(i);
if (TLI->isTypeLegal(VT)) {
const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
if (TLI->isTypeLegal(VT)) {
const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
@@
-496,7
+496,7
@@
void ResourcePriorityQueue::scheduledNode(SUnit *SU) {
// Estimate killed regs.
for (unsigned i = 0, e = ScegN->getNumOperands(); i != e; ++i) {
const SDValue &Op = ScegN->getOperand(i);
// Estimate killed regs.
for (unsigned i = 0, e = ScegN->getNumOperands(); i != e; ++i) {
const SDValue &Op = ScegN->getOperand(i);
-
EVT VT = Op.getNode()->get
ValueType(Op.getResNo());
+
MVT VT = Op.getNode()->getSimple
ValueType(Op.getResNo());
if (TLI->isTypeLegal(VT)) {
const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
if (TLI->isTypeLegal(VT)) {
const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
@@
-604,10
+604,8
@@
SUnit *ResourcePriorityQueue::pop() {
std::vector<SUnit *>::iterator Best = Queue.begin();
if (!DisableDFASched) {
signed BestCost = SUSchedulingCost(*Best);
std::vector<SUnit *>::iterator Best = Queue.begin();
if (!DisableDFASched) {
signed BestCost = SUSchedulingCost(*Best);
- for (std::vector<SUnit *>::iterator I =
Queue.begin(
),
+ for (std::vector<SUnit *>::iterator I =
llvm::next(Queue.begin()
),
E = Queue.end(); I != E; ++I) {
E = Queue.end(); I != E; ++I) {
- if (*I == *Best)
- continue;
if (SUSchedulingCost(*I) > BestCost) {
BestCost = SUSchedulingCost(*I);
if (SUSchedulingCost(*I) > BestCost) {
BestCost = SUSchedulingCost(*I);