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Switch a number of loops in lib/CodeGen over to range-based for-loops, now that
[oota-llvm.git]
/
lib
/
CodeGen
/
MachineLICM.cpp
diff --git
a/lib/CodeGen/MachineLICM.cpp
b/lib/CodeGen/MachineLICM.cpp
index ed3ed4d4d9167eb4b2c8cad6b72866ffae1b3bd3..08678f81da51fb088f625f6aca242e69921754cb 100644
(file)
--- a/
lib/CodeGen/MachineLICM.cpp
+++ b/
lib/CodeGen/MachineLICM.cpp
@@
-125,9
+125,9
@@
namespace {
initializeMachineLICMPass(*PassRegistry::getPassRegistry());
}
initializeMachineLICMPass(*PassRegistry::getPassRegistry());
}
-
virtual bool runOnMachineFunction(MachineFunction &MF)
;
+
bool runOnMachineFunction(MachineFunction &MF) override
;
- v
irtual void getAnalysisUsage(AnalysisUsage &AU) const
{
+ v
oid getAnalysisUsage(AnalysisUsage &AU) const override
{
AU.addRequired<MachineLoopInfo>();
AU.addRequired<MachineDominatorTree>();
AU.addRequired<AliasAnalysis>();
AU.addRequired<MachineLoopInfo>();
AU.addRequired<MachineDominatorTree>();
AU.addRequired<AliasAnalysis>();
@@
-136,7
+136,7
@@
namespace {
MachineFunctionPass::getAnalysisUsage(AU);
}
MachineFunctionPass::getAnalysisUsage(AU);
}
- v
irtual void releaseMemory()
{
+ v
oid releaseMemory() override
{
RegSeen.clear();
RegPressure.clear();
RegLimit.clear();
RegSeen.clear();
RegPressure.clear();
RegLimit.clear();
@@
-172,7
+172,7
@@
namespace {
BitVector &PhysRegDefs,
BitVector &PhysRegClobbers,
SmallSet<int, 32> &StoredFIs,
BitVector &PhysRegDefs,
BitVector &PhysRegClobbers,
SmallSet<int, 32> &StoredFIs,
- SmallVector
<CandidateInfo, 32
> &Candidates);
+ SmallVector
Impl<CandidateInfo
> &Candidates);
/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
/// current loop.
/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
/// current loop.
@@
-404,7
+404,7
@@
void MachineLICM::ProcessMI(MachineInstr *MI,
BitVector &PhysRegDefs,
BitVector &PhysRegClobbers,
SmallSet<int, 32> &StoredFIs,
BitVector &PhysRegDefs,
BitVector &PhysRegClobbers,
SmallSet<int, 32> &StoredFIs,
- SmallVector
<CandidateInfo, 32
> &Candidates) {
+ SmallVector
Impl<CandidateInfo
> &Candidates) {
bool RuledOut = false;
bool HasNonInvariantUse = false;
unsigned Def = 0;
bool RuledOut = false;
bool HasNonInvariantUse = false;
unsigned Def = 0;
@@
-468,12
+468,12
@@
void MachineLICM::ProcessMI(MachineInstr *MI,
for (MCRegAliasIterator AS(Reg, TRI, true); AS.isValid(); ++AS) {
if (PhysRegDefs.test(*AS))
PhysRegClobbers.set(*AS);
for (MCRegAliasIterator AS(Reg, TRI, true); AS.isValid(); ++AS) {
if (PhysRegDefs.test(*AS))
PhysRegClobbers.set(*AS);
- if (PhysRegClobbers.test(*AS))
- // MI defined register is seen defined by another instruction in
- // the loop, it cannot be a LICM candidate.
- RuledOut = true;
PhysRegDefs.set(*AS);
}
PhysRegDefs.set(*AS);
}
+ if (PhysRegClobbers.test(Reg))
+ // MI defined register is seen defined by another instruction in
+ // the loop, it cannot be a LICM candidate.
+ RuledOut = true;
}
// Only consider reloads for now and remats which do not have register
}
// Only consider reloads for now and remats which do not have register
@@
-502,7
+502,7
@@
void MachineLICM::HoistRegionPostRA() {
// Walk the entire region, count number of defs for each register, and
// collect potential LICM candidates.
// Walk the entire region, count number of defs for each register, and
// collect potential LICM candidates.
- const std::vector<MachineBasicBlock
*>
Blocks = CurLoop->getBlocks();
+ const std::vector<MachineBasicBlock
*> &
Blocks = CurLoop->getBlocks();
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
MachineBasicBlock *BB = Blocks[i];
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
MachineBasicBlock *BB = Blocks[i];
@@
-584,7
+584,7
@@
void MachineLICM::HoistRegionPostRA() {
/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
/// loop, and make sure it is not killed by any instructions in the loop.
void MachineLICM::AddToLiveIns(unsigned Reg) {
/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current
/// loop, and make sure it is not killed by any instructions in the loop.
void MachineLICM::AddToLiveIns(unsigned Reg) {
- const std::vector<MachineBasicBlock
*>
Blocks = CurLoop->getBlocks();
+ const std::vector<MachineBasicBlock
*> &
Blocks = CurLoop->getBlocks();
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
MachineBasicBlock *BB = Blocks[i];
if (!BB->isLiveIn(Reg))
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
MachineBasicBlock *BB = Blocks[i];
if (!BB->isLiveIn(Reg))
@@
-978,25
+978,23
@@
bool MachineLICM::HasLoopPHIUse(const MachineInstr *MI) const {
unsigned Reg = MO->getReg();
if (!TargetRegisterInfo::isVirtualRegister(Reg))
continue;
unsigned Reg = MO->getReg();
if (!TargetRegisterInfo::isVirtualRegister(Reg))
continue;
- for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
- UE = MRI->use_end(); UI != UE; ++UI) {
- MachineInstr *UseMI = &*UI;
+ for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
// A PHI may cause a copy to be inserted.
// A PHI may cause a copy to be inserted.
- if (UseMI
->
isPHI()) {
+ if (UseMI
.
isPHI()) {
// A PHI inside the loop causes a copy because the live range of Reg is
// extended across the PHI.
// A PHI inside the loop causes a copy because the live range of Reg is
// extended across the PHI.
- if (CurLoop->contains(UseMI))
+ if (CurLoop->contains(
&
UseMI))
return true;
// A PHI in an exit block can cause a copy to be inserted if the PHI
// has multiple predecessors in the loop with different values.
// For now, approximate by rejecting all exit blocks.
return true;
// A PHI in an exit block can cause a copy to be inserted if the PHI
// has multiple predecessors in the loop with different values.
// For now, approximate by rejecting all exit blocks.
- if (isExitBlock(UseMI
->
getParent()))
+ if (isExitBlock(UseMI
.
getParent()))
return true;
continue;
}
// Look past copies as well.
return true;
continue;
}
// Look past copies as well.
- if (UseMI
->isCopy() && CurLoop->contains(
UseMI))
- Work.push_back(UseMI);
+ if (UseMI
.isCopy() && CurLoop->contains(&
UseMI))
+ Work.push_back(
&
UseMI);
}
}
} while (!Work.empty());
}
}
} while (!Work.empty());
@@
-1011,22
+1009,20
@@
bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
return false;
if (!InstrItins || InstrItins->isEmpty() || MRI->use_nodbg_empty(Reg))
return false;
- for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
- E = MRI->use_nodbg_end(); I != E; ++I) {
- MachineInstr *UseMI = &*I;
- if (UseMI->isCopyLike())
+ for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
+ if (UseMI.isCopyLike())
continue;
continue;
- if (!CurLoop->contains(UseMI
->
getParent()))
+ if (!CurLoop->contains(UseMI
.
getParent()))
continue;
continue;
- for (unsigned i = 0, e = UseMI
->
getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = UseMI
->
getOperand(i);
+ for (unsigned i = 0, e = UseMI
.
getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = UseMI
.
getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
unsigned MOReg = MO.getReg();
if (MOReg != Reg)
continue;
if (!MO.isReg() || !MO.isUse())
continue;
unsigned MOReg = MO.getReg();
if (MOReg != Reg)
continue;
- if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i))
+ if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx,
&
UseMI, i))
return true;
}
return true;
}
@@
-1084,7
+1080,7
@@
bool MachineLICM::CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost,
return true;
for (unsigned i = BackTrace.size(); i != 0; --i) {
return true;
for (unsigned i = BackTrace.size(); i != 0; --i) {
- SmallVector
<unsigned, 8
> &RP = BackTrace[i-1];
+ SmallVector
Impl<unsigned
> &RP = BackTrace[i-1];
if (RP[RCId] + Cost >= Limit)
return true;
}
if (RP[RCId] + Cost >= Limit)
return true;
}
@@
-1130,7
+1126,7
@@
void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
// Update register pressure of blocks from loop header to current block.
for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) {
// Update register pressure of blocks from loop header to current block.
for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) {
- SmallVector
<unsigned, 8
> &RP = BackTrace[i];
+ SmallVector
Impl<unsigned
> &RP = BackTrace[i];
for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
CI != CE; ++CI) {
unsigned RCId = CI->first;
for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
CI != CE; ++CI) {
unsigned RCId = CI->first;