- DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
- LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
-
- // Virtual registers may be defined multiple times (due to phi
- // elimination and 2-addr elimination). Much of what we do only has to be
- // done once for the vreg. We use an empty interval to detect the first
- // time we see a vreg.
- if (interval.empty()) {
- // Get the Idx of the defining instructions.
- unsigned defIndex = getDefIndex(getInstructionIndex(mi));
-
- unsigned ValNum = interval.getNextValue();
- assert(ValNum == 0 && "First value in interval is not 0?");
- ValNum = 0; // Clue in the optimizer.
-
- // Loop over all of the blocks that the vreg is defined in. There are
- // two cases we have to handle here. The most common case is a vreg
- // whose lifetime is contained within a basic block. In this case there
- // will be a single kill, in MBB, which comes after the definition.
- if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
- // FIXME: what about dead vars?
- unsigned killIdx;
- if (vi.Kills[0] != mi)
- killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
- else
- killIdx = defIndex+1;
-
- // If the kill happens after the definition, we have an intra-block
- // live range.
- if (killIdx > defIndex) {
- assert(vi.AliveBlocks.empty() &&
- "Shouldn't be alive across any blocks!");
- LiveRange LR(defIndex, killIdx, ValNum);
- interval.addRange(LR);
- DEBUG(std::cerr << " +" << LR << "\n");
- return;
- }
- }
-
- // The other case we handle is when a virtual register lives to the end
- // of the defining block, potentially live across some blocks, then is
- // live into some number of blocks, but gets killed. Start by adding a
- // range that goes from this definition to the end of the defining block.
- LiveRange NewLR(defIndex, getInstructionIndex(&mbb->back()) +
- InstrSlots::NUM, ValNum);
- DEBUG(std::cerr << " +" << NewLR);
- interval.addRange(NewLR);
-
- // Iterate over all of the blocks that the variable is completely
- // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
- // live interval.
- for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
- if (vi.AliveBlocks[i]) {
- MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
- if (!mbb->empty()) {
- LiveRange LR(getInstructionIndex(&mbb->front()),
- getInstructionIndex(&mbb->back())+InstrSlots::NUM,
- ValNum);
- interval.addRange(LR);
- DEBUG(std::cerr << " +" << LR);
- }
- }
- }
-
- // Finally, this virtual register is live from the start of any killing
- // block to the 'use' slot of the killing instruction.
- for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
- MachineInstr *Kill = vi.Kills[i];
- LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
- getUseIndex(getInstructionIndex(Kill))+1, ValNum);
- interval.addRange(LR);
- DEBUG(std::cerr << " +" << LR);
- }
+ DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg));
+ LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
+
+ // Virtual registers may be defined multiple times (due to phi
+ // elimination and 2-addr elimination). Much of what we do only has to be
+ // done once for the vreg. We use an empty interval to detect the first
+ // time we see a vreg.
+ if (interval.empty()) {
+ // Get the Idx of the defining instructions.
+ unsigned defIndex = getDefIndex(getInstructionIndex(mi));
+
+ unsigned ValNum = interval.getNextValue();
+ assert(ValNum == 0 && "First value in interval is not 0?");
+ ValNum = 0; // Clue in the optimizer.
+
+ // Loop over all of the blocks that the vreg is defined in. There are
+ // two cases we have to handle here. The most common case is a vreg
+ // whose lifetime is contained within a basic block. In this case there
+ // will be a single kill, in MBB, which comes after the definition.
+ if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
+ // FIXME: what about dead vars?
+ unsigned killIdx;
+ if (vi.Kills[0] != mi)
+ killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
+ else
+ killIdx = defIndex+1;
+
+ // If the kill happens after the definition, we have an intra-block
+ // live range.
+ if (killIdx > defIndex) {
+ assert(vi.AliveBlocks.empty() &&
+ "Shouldn't be alive across any blocks!");
+ LiveRange LR(defIndex, killIdx, ValNum);
+ interval.addRange(LR);
+ DEBUG(std::cerr << " +" << LR << "\n");
+ return;
+ }
+ }
+
+ // The other case we handle is when a virtual register lives to the end
+ // of the defining block, potentially live across some blocks, then is
+ // live into some number of blocks, but gets killed. Start by adding a
+ // range that goes from this definition to the end of the defining block.
+ LiveRange NewLR(defIndex, getInstructionIndex(&mbb->back()) +
+ InstrSlots::NUM, ValNum);
+ DEBUG(std::cerr << " +" << NewLR);
+ interval.addRange(NewLR);
+
+ // Iterate over all of the blocks that the variable is completely
+ // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
+ // live interval.
+ for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
+ if (vi.AliveBlocks[i]) {
+ MachineBasicBlock* mbb = mf_->getBlockNumbered(i);
+ if (!mbb->empty()) {
+ LiveRange LR(getInstructionIndex(&mbb->front()),
+ getInstructionIndex(&mbb->back())+InstrSlots::NUM,
+ ValNum);
+ interval.addRange(LR);
+ DEBUG(std::cerr << " +" << LR);
+ }
+ }
+ }
+
+ // Finally, this virtual register is live from the start of any killing
+ // block to the 'use' slot of the killing instruction.
+ for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
+ MachineInstr *Kill = vi.Kills[i];
+ LiveRange LR(getInstructionIndex(Kill->getParent()->begin()),
+ getUseIndex(getInstructionIndex(Kill))+1, ValNum);
+ interval.addRange(LR);
+ DEBUG(std::cerr << " +" << LR);
+ }
+
+ } else {
+ // If this is the second time we see a virtual register definition, it
+ // must be due to phi elimination or two addr elimination. If this is
+ // the result of two address elimination, then the vreg is the first
+ // operand, and is a def-and-use.
+ if (mi->getOperand(0).isRegister() &&
+ mi->getOperand(0).getReg() == interval.reg &&
+ mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) {
+ // If this is a two-address definition, then we have already processed
+ // the live range. The only problem is that we didn't realize there
+ // are actually two values in the live interval. Because of this we
+ // need to take the LiveRegion that defines this register and split it
+ // into two values.
+ unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
+ unsigned RedefIndex = getDefIndex(getInstructionIndex(mi));
+
+ // Delete the initial value, which should be short and continuous,
+ // becuase the 2-addr copy must be in the same MBB as the redef.
+ interval.removeRange(DefIndex, RedefIndex);
+
+ LiveRange LR(DefIndex, RedefIndex, interval.getNextValue());
+ DEBUG(std::cerr << " replace range with " << LR);
+ interval.addRange(LR);
+
+ // If this redefinition is dead, we need to add a dummy unit live
+ // range covering the def slot.
+ for (LiveVariables::killed_iterator KI = lv_->dead_begin(mi),
+ E = lv_->dead_end(mi); KI != E; ++KI)
+ if (KI->second == interval.reg) {
+ interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
+ break;
+ }
+
+ DEBUG(std::cerr << "RESULT: " << interval);