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Changes For Bug 352
[oota-llvm.git]
/
lib
/
CodeGen
/
InstrSched
/
SchedGraph.cpp
diff --git
a/lib/CodeGen/InstrSched/SchedGraph.cpp
b/lib/CodeGen/InstrSched/SchedGraph.cpp
index 379fbfe8a7c174dbf3ae2fdf1d145113a010d13e..00b48d537d3eee8089fb54d58f2dd5fd1ee442b6 100644
(file)
--- a/
lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/
lib/CodeGen/InstrSched/SchedGraph.cpp
@@
-15,13
+15,15
@@
#include "SchedGraph.h"
#include "llvm/Function.h"
#include "SchedGraph.h"
#include "llvm/Function.h"
-#include "llvm/iOther.h"
-#include "llvm/CodeGen/MachineCodeForInstruction.h"
+#include "llvm/Instructions.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegInfo.h"
-#include "Support/STLExtras.h"
+#include "../../Target/SparcV9/MachineCodeForInstruction.h"
+#include "../../Target/SparcV9/SparcV9RegInfo.h"
+#include "../../Target/SparcV9/SparcV9InstrInfo.h"
+#include "llvm/ADT/STLExtras.h"
+#include <iostream>
namespace llvm {
namespace llvm {
@@
-60,9
+62,9
@@
SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
MI = I;
MachineOpCode mopCode = MI->getOpcode();
MI = I;
MachineOpCode mopCode = MI->getOpcode();
- latency = Target.getInstrInfo()
.
hasResultInterlock(mopCode)
- ? Target.getInstrInfo()
.
minLatency(mopCode)
- : Target.getInstrInfo()
.
maxLatency(mopCode);
+ latency = Target.getInstrInfo()
->
hasResultInterlock(mopCode)
+ ? Target.getInstrInfo()
->
minLatency(mopCode)
+ : Target.getInstrInfo()
->
maxLatency(mopCode);
}
}
}
}
@@
-106,7
+108,7
@@
SchedGraph::~SchedGraph() {
void SchedGraph::dump() const {
std::cerr << " Sched Graph for Basic Block: "
<< MBB.getBasicBlock()->getName()
void SchedGraph::dump() const {
std::cerr << " Sched Graph for Basic Block: "
<< MBB.getBasicBlock()->getName()
- << " (" << MBB.getBasicBlock() << ")"
+ << " (" <<
*
MBB.getBasicBlock() << ")"
<< "\n\n Actual Root nodes: ";
for (SchedGraphNodeCommon::const_iterator I = graphRoot->beginOutEdges(),
E = graphRoot->endOutEdges();
<< "\n\n Actual Root nodes: ";
for (SchedGraphNodeCommon::const_iterator I = graphRoot->beginOutEdges(),
E = graphRoot->endOutEdges();
@@
-138,7
+140,7
@@
void SchedGraph::addDummyEdges() {
void SchedGraph::addCDEdges(const TerminatorInst* term,
const TargetMachine& target) {
void SchedGraph::addCDEdges(const TerminatorInst* term,
const TargetMachine& target) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii =
*
target.getInstrInfo();
MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
// Find the first branch instr in the sequence of machine instrs for term
MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
// Find the first branch instr in the sequence of machine instrs for term
@@
-240,7
+242,7
@@
static const unsigned int SG_DepOrderArray[][3] = {
//
void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
const TargetMachine& target) {
//
void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
const TargetMachine& target) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii =
*
target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
@@
-272,7
+274,7
@@
void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
//
void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
const TargetMachine& target) {
//
void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
const TargetMachine& target) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii =
*
target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
@@
-471,7
+473,7
@@
void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
std::vector<SchedGraphNode*>& callDepNodeVec,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap) {
std::vector<SchedGraphNode*>& callDepNodeVec,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii =
*
target.getInstrInfo();
MachineOpCode opCode = node->getOpcode();
MachineOpCode opCode = node->getOpcode();
@@
-493,7
+495,7
@@
void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
unsigned regNum = mop.getReg();
// If this is not a dummy zero register, record the reference in order
unsigned regNum = mop.getReg();
// If this is not a dummy zero register, record the reference in order
- if (regNum != target.getRegInfo()
.
getZeroRegNum())
+ if (regNum != target.getRegInfo()
->
getZeroRegNum())
regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i));
regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i));
@@
-502,8
+504,8
@@
void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node)
{
unsigned rcid;
if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node)
{
unsigned rcid;
- int regInClass = target.getRegInfo()
.
getClassRegNum(regNum, rcid);
- if (target.getRegInfo()
.
getMachineRegClass(rcid)
+ int regInClass = target.getRegInfo()
->
getClassRegNum(regNum, rcid);
+ if (target.getRegInfo()
->
getMachineRegClass(rcid)
->isRegVolatile(regInClass))
callDepNodeVec.push_back(node);
}
->isRegVolatile(regInClass))
callDepNodeVec.push_back(node);
}
@@
-532,7
+534,7
@@
void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
const MachineOperand& mop = MI.getImplicitOp(i);
if (mop.hasAllocatedReg()) {
unsigned regNum = mop.getReg();
const MachineOperand& mop = MI.getImplicitOp(i);
if (mop.hasAllocatedReg()) {
unsigned regNum = mop.getReg();
- if (regNum != target.getRegInfo()
.
getZeroRegNum())
+ if (regNum != target.getRegInfo()
->
getZeroRegNum())
regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i + MI.getNumOperands()));
continue; // nothing more to do
regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i + MI.getNumOperands()));
continue; // nothing more to do
@@
-553,14
+555,14
@@
void SchedGraph::buildNodesForBB(const TargetMachine& target,
std::vector<SchedGraphNode*>& callDepNodeVec,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap) {
std::vector<SchedGraphNode*>& callDepNodeVec,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap) {
- const TargetInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii =
*
target.getInstrInfo();
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
unsigned i = 0;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
++I, ++i)
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
unsigned i = 0;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
++I, ++i)
- if (
!mii.isDummyPhiInstr(I->getOpcode())
) {
+ if (
I->getOpcode() != V9::PHI
) {
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
noteGraphNodeForInstr(I, node);
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
noteGraphNodeForInstr(I, node);
@@
-693,7
+695,7
@@
void SchedGraphEdge::print(std::ostream &os) const {
os<< "Control Dep";
break;
case SchedGraphEdge::ValueDep:
os<< "Control Dep";
break;
case SchedGraphEdge::ValueDep:
- os<< "Reg Value " << val;
+ os<< "Reg Value " <<
*
val;
break;
case SchedGraphEdge::MemoryDep:
os<< "Memory Dep";
break;
case SchedGraphEdge::MemoryDep:
os<< "Memory Dep";