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Fix (bitcast (fabs x)), (bitcast (fneg x)) and (bitcast (fcopysign cst,
[oota-llvm.git]
/
lib
/
CodeGen
/
AllocationOrder.cpp
diff --git
a/lib/CodeGen/AllocationOrder.cpp
b/lib/CodeGen/AllocationOrder.cpp
index 94754a0d35a81785c4d06d49e166ce6149bb87ad..40451c0d6c19dcaf8230b63ad714554f8e3c33bd 100644
(file)
--- a/
lib/CodeGen/AllocationOrder.cpp
+++ b/
lib/CodeGen/AllocationOrder.cpp
@@
-14,7
+14,6
@@
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "regalloc"
#include "AllocationOrder.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "AllocationOrder.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@
-22,19
+21,21
@@
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetMachine.h"
using namespace llvm;
using namespace llvm;
+#define DEBUG_TYPE "regalloc"
+
// Compare VirtRegMap::getRegAllocPref().
AllocationOrder::AllocationOrder(unsigned VirtReg,
const VirtRegMap &VRM,
// Compare VirtRegMap::getRegAllocPref().
AllocationOrder::AllocationOrder(unsigned VirtReg,
const VirtRegMap &VRM,
- const RegisterClassInfo &RegClassInfo)
+ const RegisterClassInfo &RegClassInfo,
+ const LiveRegMatrix *Matrix)
: Pos(0) {
const MachineFunction &MF = VRM.getMachineFunction();
const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
: Pos(0) {
const MachineFunction &MF = VRM.getMachineFunction();
const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
- TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
+ TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM
, Matrix
);
rewind();
DEBUG({
rewind();
DEBUG({
@@
-45,4
+46,9
@@
AllocationOrder::AllocationOrder(unsigned VirtReg,
dbgs() << '\n';
}
});
dbgs() << '\n';
}
});
+#ifndef NDEBUG
+ for (unsigned I = 0, E = Hints.size(); I != E; ++I)
+ assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() &&
+ "Target hint is outside allocation order.");
+#endif
}
}