+ /// Return a bitmask representing the parts of a register that are covered by
+ /// SubIdx \see LaneBitmask.
+ ///
+ /// SubIdx == 0 is allowed, it has the lane mask ~0u.
+ LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
+ assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
+ return SubRegIndexLaneMasks[SubIdx];
+ }
+
+ /// Returns true if the given lane mask is imprecise.
+ ///
+ /// LaneMasks as given by getSubRegIndexLaneMask() have a limited number of
+ /// bits, so for targets with more than 31 disjunct subregister indices there
+ /// may be cases where:
+ /// getSubReg(Reg,A) does not overlap getSubReg(Reg,B)
+ /// but we still have
+ /// (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0.
+ /// This function returns true in those cases.
+ static bool isImpreciseLaneMask(LaneBitmask LaneMask) {
+ return LaneMask & 0x80000000u;
+ }
+
+ /// The lane masks returned by getSubRegIndexLaneMask() above can only be
+ /// used to determine if sub-registers overlap - they can't be used to
+ /// determine if a set of sub-registers completely cover another
+ /// sub-register.
+ ///
+ /// The X86 general purpose registers have two lanes corresponding to the
+ /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
+ /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
+ /// sub_32bit sub-register.
+ ///
+ /// On the other hand, the ARM NEON lanes fully cover their registers: The
+ /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
+ /// This is related to the CoveredBySubRegs property on register definitions.
+ ///
+ /// This function returns a bit mask of lanes that completely cover their
+ /// sub-registers. More precisely, given:
+ ///
+ /// Covering = getCoveringLanes();
+ /// MaskA = getSubRegIndexLaneMask(SubA);
+ /// MaskB = getSubRegIndexLaneMask(SubB);
+ ///
+ /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
+ /// SubB.
+ LaneBitmask getCoveringLanes() const { return CoveringLanes; }
+