+ bool allowsUnalignedMemoryAccesses() const {
+ return allowUnalignedMemoryAccesses;
+ }
+
+ /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
+ /// to implement llvm.setjmp.
+ bool usesUnderscoreSetJmp() const {
+ return UseUnderscoreSetJmp;
+ }
+
+ /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
+ /// to implement llvm.longjmp.
+ bool usesUnderscoreLongJmp() const {
+ return UseUnderscoreLongJmp;
+ }
+
+ /// getStackPointerRegisterToSaveRestore - If a physical register, this
+ /// specifies the register that llvm.savestack/llvm.restorestack should save
+ /// and restore.
+ unsigned getStackPointerRegisterToSaveRestore() const {
+ return StackPointerRegisterToSaveRestore;
+ }
+
+ /// getExceptionAddressRegister - If a physical register, this returns
+ /// the register that receives the exception address on entry to a landing
+ /// pad.
+ unsigned getExceptionAddressRegister() const {
+ return ExceptionPointerRegister;
+ }
+
+ /// getExceptionSelectorRegister - If a physical register, this returns
+ /// the register that receives the exception typeid on entry to a landing
+ /// pad.
+ unsigned getExceptionSelectorRegister() const {
+ return ExceptionSelectorRegister;
+ }
+
+ /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
+ /// set, the default is 200)
+ unsigned getJumpBufSize() const {
+ return JumpBufSize;
+ }
+
+ /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
+ /// (if never set, the default is 0)
+ unsigned getJumpBufAlignment() const {
+ return JumpBufAlignment;
+ }
+
+ /// getPreIndexedAddressParts - returns true by value, base pointer and
+ /// offset pointer and addressing mode by reference if the node's address
+ /// can be legally represented as pre-indexed load / store address.
+ virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
+ SDOperand &Offset,
+ ISD::MemIndexedMode &AM,
+ SelectionDAG &DAG) {
+ return false;
+ }
+
+ /// getPostIndexedAddressParts - returns true by value, base pointer and
+ /// offset pointer and addressing mode by reference if this node can be
+ /// combined with a load / store to form a post-indexed load / store.
+ virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
+ SDOperand &Base, SDOperand &Offset,
+ ISD::MemIndexedMode &AM,
+ SelectionDAG &DAG) {
+ return false;
+ }
+
+ //===--------------------------------------------------------------------===//
+ // TargetLowering Optimization Methods
+ //
+
+ /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
+ /// SDOperands for returning information from TargetLowering to its clients
+ /// that want to combine
+ struct TargetLoweringOpt {
+ SelectionDAG &DAG;
+ SDOperand Old;
+ SDOperand New;
+
+ TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
+
+ bool CombineTo(SDOperand O, SDOperand N) {
+ Old = O;
+ New = N;
+ return true;
+ }
+
+ /// ShrinkDemandedConstant - Check to see if the specified operand of the
+ /// specified instruction is a constant integer. If so, check to see if there
+ /// are any bits set in the constant that are not demanded. If so, shrink the
+ /// constant and return true.
+ bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
+ };
+
+ /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
+ /// use this predicate to simplify operations downstream. Op and Mask are
+ /// known to be the same type.
+ bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
+ const;
+
+ /// ComputeMaskedBits - Determine which of the bits specified in Mask are
+ /// known to be either zero or one and return them in the KnownZero/KnownOne
+ /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
+ /// processing. Targets can implement the computeMaskedBitsForTargetNode
+ /// method, to allow target nodes to be understood.
+ void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero,
+ uint64_t &KnownOne, unsigned Depth = 0) const;
+
+ /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
+ /// DemandedMask bits of the result of Op are ever used downstream. If we can
+ /// use this information to simplify Op, create a new simplified DAG node and
+ /// return true, returning the original and new nodes in Old and New.
+ /// Otherwise, analyze the expression and return a mask of KnownOne and
+ /// KnownZero bits for the expression (used to simplify the caller).
+ /// The KnownZero/One bits may only be accurate for those bits in the
+ /// DemandedMask.
+ bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
+ uint64_t &KnownZero, uint64_t &KnownOne,
+ TargetLoweringOpt &TLO, unsigned Depth = 0) const;
+
+ /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
+ /// Mask are known to be either zero or one and return them in the
+ /// KnownZero/KnownOne bitsets.
+ virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+ uint64_t Mask,
+ uint64_t &KnownZero,
+ uint64_t &KnownOne,
+ unsigned Depth = 0) const;
+
+ /// ComputeNumSignBits - Return the number of times the sign bit of the
+ /// register is replicated into the other bits. We know that at least 1 bit
+ /// is always equal to the sign bit (itself), but other cases can give us
+ /// information. For example, immediately after an "SRA X, 2", we know that
+ /// the top 3 bits are all equal to each other, so we return 3.
+ unsigned ComputeNumSignBits(SDOperand Op, unsigned Depth = 0) const;
+
+ /// ComputeNumSignBitsForTargetNode - This method can be implemented by
+ /// targets that want to expose additional information about sign bits to the
+ /// DAG Combiner.
+ virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
+ unsigned Depth = 0) const;
+
+ struct DAGCombinerInfo {
+ void *DC; // The DAG Combiner object.
+ bool BeforeLegalize;
+ bool CalledByLegalizer;
+ public:
+ SelectionDAG &DAG;
+
+ DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
+ : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
+
+ bool isBeforeLegalize() const { return BeforeLegalize; }
+ bool isCalledByLegalizer() const { return CalledByLegalizer; }
+
+ void AddToWorklist(SDNode *N);
+ SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
+ SDOperand CombineTo(SDNode *N, SDOperand Res);
+ SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
+ };
+
+ /// SimplifySetCC - Try to simplify a setcc built with the specified operands
+ /// and cc. If it is unable to simplify it, return a null SDOperand.
+ SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
+ ISD::CondCode Cond, bool foldBooleans,
+ DAGCombinerInfo &DCI) const;