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Allow memory intrinsics to be tail calls
[oota-llvm.git]
/
include
/
llvm
/
CodeGen
/
LiveVariables.h
diff --git
a/include/llvm/CodeGen/LiveVariables.h
b/include/llvm/CodeGen/LiveVariables.h
index 71062a2a51965594c147955fa742e37d95b99c15..55b97dc3e71d94306be66c173fb50e4f56a36c3a 100644
(file)
--- a/
include/llvm/CodeGen/LiveVariables.h
+++ b/
include/llvm/CodeGen/LiveVariables.h
@@
-29,21
+29,19
@@
#ifndef LLVM_CODEGEN_LIVEVARIABLES_H
#define LLVM_CODEGEN_LIVEVARIABLES_H
#ifndef LLVM_CODEGEN_LIVEVARIABLES_H
#define LLVM_CODEGEN_LIVEVARIABLES_H
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseBitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseBitVector.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
namespace llvm {
+class MachineBasicBlock;
class MachineRegisterInfo;
class MachineRegisterInfo;
-class TargetRegisterInfo;
class LiveVariables : public MachineFunctionPass {
public:
class LiveVariables : public MachineFunctionPass {
public:
@@
-126,12
+124,6
@@
private:
/// building live intervals.
SparseBitVector<> PHIJoins;
/// building live intervals.
SparseBitVector<> PHIJoins;
- /// ReservedRegisters - This vector keeps track of which registers
- /// are reserved register which are not allocatable by the target machine.
- /// We can not track liveness for values that are in this set.
- ///
- BitVector ReservedRegisters;
-
private: // Intermediate data structures
MachineFunction *MF;
private: // Intermediate data structures
MachineFunction *MF;
@@
-142,14
+134,14
@@
private: // Intermediate data structures
// PhysRegInfo - Keep track of which instruction was the last def of a
// physical register. This is a purely local property, because all physical
// register references are presumed dead across basic blocks.
// PhysRegInfo - Keep track of which instruction was the last def of a
// physical register. This is a purely local property, because all physical
// register references are presumed dead across basic blocks.
-
MachineInstr **
PhysRegDef;
+
std::vector<MachineInstr *>
PhysRegDef;
// PhysRegInfo - Keep track of which instruction was the last use of a
// physical register. This is a purely local property, because all physical
// register references are presumed dead across basic blocks.
// PhysRegInfo - Keep track of which instruction was the last use of a
// physical register. This is a purely local property, because all physical
// register references are presumed dead across basic blocks.
-
MachineInstr **
PhysRegUse;
+
std::vector<MachineInstr *>
PhysRegUse;
-
SmallVector<unsigned, 4> *
PHIVarInfo;
+
std::vector<SmallVector<unsigned, 4>>
PHIVarInfo;
// DistanceMap - Keep track the distance of a MI from the start of the
// current basic block.
// DistanceMap - Keep track the distance of a MI from the start of the
// current basic block.
@@
-160,10
+152,13
@@
private: // Intermediate data structures
/// the last use of the whole register.
bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
/// the last use of the whole register.
bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
+ /// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask.
+ void HandleRegMask(const MachineOperand&);
+
void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
- SmallVector
<unsigned, 4
> &Defs);
- void UpdatePhysRegDefs(MachineInstr *MI, SmallVector
<unsigned, 4
> &Defs);
+ SmallVector
Impl<unsigned
> &Defs);
+ void UpdatePhysRegDefs(MachineInstr *MI, SmallVector
Impl<unsigned
> &Defs);
/// FindLastRefOrPartRef - Return the last reference or partial reference of
/// the specified register.
/// FindLastRefOrPartRef - Return the last reference or partial reference of
/// the specified register.
@@
-180,9
+175,13
@@
private: // Intermediate data structures
/// register which is used in a PHI node. We map that to the BB the vreg
/// is coming from.
void analyzePHINodes(const MachineFunction& Fn);
/// register which is used in a PHI node. We map that to the BB the vreg
/// is coming from.
void analyzePHINodes(const MachineFunction& Fn);
+
+ void runOnInstr(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
+
+ void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
public:
public:
-
virtual bool runOnMachineFunction(MachineFunction &MF)
;
+
bool runOnMachineFunction(MachineFunction &MF) override
;
/// RegisterDefIsDead - Return true if the specified instruction defines the
/// specified register, but that definition is dead.
/// RegisterDefIsDead - Return true if the specified instruction defines the
/// specified register, but that definition is dead.
@@
-263,10
+262,10
@@
public:
(void)Removed;
return true;
}
(void)Removed;
return true;
}
-
- void getAnalysisUsage(AnalysisUsage &AU) const;
- virtual void releaseMemory() {
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+ void releaseMemory() override {
VirtRegInfo.clear();
}
VirtRegInfo.clear();
}