+static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req)
+{
+ int Src0MemSize, DstMemSize, Src1MemSize;
+ unsigned long Src0Start, Src1Start, DstStart;
+ unsigned long Src0PageCount, Src1PageCount, DstPageCount;
+ uint32_t AllSize;
+ uint32_t *MMU_Base, *MMU_Base_phys;
+ int ret;
+ int status;
+ uint32_t uv_size, v_size;
+ struct page **pages = NULL;
+ MMU_Base = NULL;
+ Src0MemSize = 0;
+ Src1MemSize = 0;
+ DstMemSize = 0;
+ Src0PageCount = 0;
+ Src1PageCount = 0;
+ DstPageCount = 0;
+
+ /* cal src0 buf mmu info */
+ if (req->mmu_info.src0_mmu_flag & 1) {
+ Src0PageCount = rga2_buf_size_cal(req->src.yrgb_addr,
+ req->src.uv_addr,
+ req->src.v_addr,
+ req->src.format,
+ req->src.vir_w,
+ (req->src.vir_h),
+ &Src0Start);
+ if (Src0PageCount == 0)
+ return -EINVAL;
+ }
+ /* cal src1 buf mmu info */
+ if (req->mmu_info.src1_mmu_flag & 1) {
+ Src1PageCount = rga2_buf_size_cal(req->src1.yrgb_addr,
+ req->src1.uv_addr,
+ req->src1.v_addr,
+ req->src1.format,
+ req->src1.vir_w,
+ (req->src1.vir_h),
+ &Src1Start);
+ Src1PageCount = (Src1PageCount + 3) & (~3);
+ if (Src1PageCount == 0)
+ return -EINVAL;
+ }
+ /* cal dst buf mmu info */
+ if (req->mmu_info.dst_mmu_flag & 1) {
+ DstPageCount = rga2_buf_size_cal(req->dst.yrgb_addr,
+ req->dst.uv_addr,
+ req->dst.v_addr,
+ req->dst.format,
+ req->dst.vir_w,
+ req->dst.vir_h,
+ &DstStart);
+ if (DstPageCount == 0)
+ return -EINVAL;
+ }
+ /* Cal out the needed mem size */
+ Src0MemSize = (Src0PageCount + 15) & (~15);
+ Src1MemSize = (Src1PageCount + 15) & (~15);
+ DstMemSize = (DstPageCount + 15) & (~15);
+ AllSize = Src0MemSize + Src1MemSize + DstMemSize;
+
+ if (rga2_mmu_buf_get_try(&rga2_mmu_buf, AllSize)) {
+ pr_err("RGA2 Get MMU mem failed\n");
+ status = RGA2_MALLOC_ERROR;
+ goto out;
+ }
+ pages = rga2_mmu_buf.pages;
+ mutex_lock(&rga2_service.lock);
+ MMU_Base = rga2_mmu_buf.buf_virtual +
+ (rga2_mmu_buf.front & (rga2_mmu_buf.size - 1));
+ MMU_Base_phys = rga2_mmu_buf.buf +
+ (rga2_mmu_buf.front & (rga2_mmu_buf.size - 1));
+ mutex_unlock(&rga2_service.lock);
+ if (Src0MemSize) {
+ if (req->sg_src0)
+ ret = rga2_MapION(req->sg_src0,
+ &MMU_Base[0], Src0MemSize);
+ else
+ ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0],
+ Src0Start, Src0PageCount, 0);
+
+ if (ret < 0) {
+ pr_err("rga2 map src0 memory failed\n");
+ status = ret;
+ goto out;
+ }
+ /* change the buf address in req struct */
+ req->mmu_info.src0_base_addr = (((unsigned long)MMU_Base_phys));
+ uv_size = (req->src.uv_addr
+ - (Src0Start << PAGE_SHIFT)) >> PAGE_SHIFT;
+ v_size = (req->src.v_addr
+ - (Src0Start << PAGE_SHIFT)) >> PAGE_SHIFT;
+
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK));
+ req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) |
+ (uv_size << PAGE_SHIFT);
+ req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) |
+ (v_size << PAGE_SHIFT);
+ }
+ if (Src1MemSize) {
+ if (req->sg_src1)
+ ret = rga2_MapION(req->sg_src1,
+ MMU_Base + Src0MemSize, Src1MemSize);
+ else
+ ret = rga2_MapUserMemory(&pages[0],
+ MMU_Base + Src0MemSize,
+ Src1Start, Src1PageCount, 0);
+ if (ret < 0) {
+ pr_err("rga2 map src1 memory failed\n");
+ status = ret;
+ goto out;
+ }
+ /* change the buf address in req struct */
+ req->mmu_info.src1_base_addr = ((unsigned long)(MMU_Base_phys
+ + Src0MemSize));
+ req->src1.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK));
+ }
+ if (DstMemSize) {
+ if (req->sg_dst)
+ ret = rga2_MapION(req->sg_dst, MMU_Base + Src0MemSize
+ + Src1MemSize, DstMemSize);
+ else
+ ret = rga2_MapUserMemory(&pages[0], MMU_Base
+ + Src0MemSize + Src1MemSize,
+ DstStart, DstPageCount, 1);
+ if (ret < 0) {
+ pr_err("rga2 map dst memory failed\n");
+ status = ret;
+ goto out;
+ }
+ /* change the buf address in req struct */
+ req->mmu_info.dst_base_addr = ((unsigned long)(MMU_Base_phys
+ + Src0MemSize + Src1MemSize));
+ req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK));
+ uv_size = (req->dst.uv_addr
+ - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
+ v_size = (req->dst.v_addr
+ - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
+ req->dst.uv_addr = (req->dst.uv_addr & (~PAGE_MASK)) |
+ ((uv_size) << PAGE_SHIFT);
+ req->dst.v_addr = (req->dst.v_addr & (~PAGE_MASK)) |
+ ((v_size) << PAGE_SHIFT);
+
+ if (((req->alpha_rop_flag & 1) == 1) && (req->bitblt_mode == 0)) {
+ req->mmu_info.src1_base_addr = req->mmu_info.dst_base_addr;
+ req->mmu_info.src1_mmu_flag = req->mmu_info.dst_mmu_flag;
+ }
+ }
+ /* flush data to DDR */
+ rga_dma_flush_range(MMU_Base, (MMU_Base + AllSize));
+ rga2_mmu_buf_get(&rga2_mmu_buf, AllSize);
+ reg->MMU_len = AllSize;
+ status = 0;
+out:
+ return status;
+}
+
+static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_req *req)\r
+{\r
+ int SrcMemSize, DstMemSize;\r
+ unsigned long SrcStart, DstStart;\r