-AArch64 target
---------------
-
-We've added support for AArch64, ARM's 64-bit architecture. Development is still
-in fairly early stages, but we expect successful compilation when:
-
-- compiling standard compliant C99 and C++03 with Clang;
-- using Linux as a target platform;
-- where code + static data doesn't exceed 4GB in size (heap allocated data has
- no limitation).
-
-Some additional functionality is also implemented, notably DWARF debugging,
-GNU-style thread local storage and inline assembly.
-
-Hexagon Target
---------------
-
-- Removed support for hexagonv2 and hexagonv3 processor architectures.
-
-Loop Vectorizer
----------------
-
-We've continued the work on the loop vectorizer. The loop vectorizer now
-has the following features:
-
-- Loops with unknown trip count.
-- Runtime checks of pointers
-- Reductions, Inductions
-- If Conversion
-- Pointer induction variables
-- Reverse iterators
-- Vectorization of mixed types
-- Vectorization of function calls
-- Partial unrolling during vectorization
-
-R600 Backend
-------------
-
-The R600 backend was added in this release, it supports AMD GPUs
-(HD2XXX - HD7XXX). This backend is used in AMD's Open Source
-graphics / compute drivers which are developed as part of the `Mesa3D
-<http://www.mesa3d.org>`_ project.
-
+Changes to the ARM Backend
+--------------------------
+
+Since release 3.3, a lot of new features have been included in the ARM
+back-end but weren't production ready (ie. well tested) on release 3.4.
+Just after the 3.4 release, we started heavily testing two major parts
+of the back-end: the integrated assembler (IAS) and the ARM exception
+handling (EHABI), and now they are enabled by default on LLVM/Clang.
+
+The IAS received a lot of GNU extensions and directives, as well as some
+specific pre-UAL instructions. Not all remaining directives will be
+implemented, as we made judgement calls on the need versus the complexity,
+and have chosen simplicity and future compatibility where hard decisions
+had to be made. The major difference is, as stated above, the IAS validates
+all inline ASM, not just for object emission, and that cause trouble with
+some uses of inline ASM as pre-processor magic.
+
+So, while the IAS is good enough to compile large projects (including most
+of the Linux kernel), there are a few things that we can't (and probably
+won't) do. For those cases, please use ``-fno-integrated-as`` in Clang.
+
+Exception handling is another big change. After extensive testing and
+changes to cooperate with Dwarf unwinding, EHABI is enabled by default.
+The options ``-arm-enable-ehabi`` and ``-arm-enable-ehabi-descriptors``,
+which were used to enable EHABI in the previous releases, are removed now.
+
+This means all ARM code will emit EH unwind tables, or CFI unwinding (for
+debug/profiling), or both. To avoid run-time inconsistencies, C code will
+also emit EH tables (in case they interoperate with C++ code), as is the
+case for other architectures (ex. x86_64).
+
+Changes to the MIPS Target
+--------------------------
+
+There has been a large amount of improvements to the MIPS target which can be
+broken down into subtarget, ABI, and Integrated Assembler changes.
+
+Subtargets
+^^^^^^^^^^
+
+Added support for Release 6 of the MIPS32 and MIPS64 architecture (MIPS32r6
+and MIPS64r6). Release 6 makes a number of significant changes to the MIPS32
+and MIPS64 architectures. For example, FPU registers are always 64-bits wide,
+FPU NaN values conform to IEEE 754 (2008), and the unaligned memory instructions
+(such as lwl and lwr) have been replaced with a requirement for ordinary memory
+operations to support unaligned operations. Full details of MIPS32 and MIPS64
+Release 6 can be found on the `MIPS64 Architecture page at Imagination
+Technologies <http://www.imgtec.com/mips/architectures/mips64.asp>`_.
+
+This release also adds experimental support for MIPS-IV, cnMIPS, and Cavium
+Octeon CPU's.
+
+Support for the MIPS SIMD Architecture (MSA) has been improved to support MSA
+on MIPS64.
+
+Support for IEEE 754 (2008) NaN values has been added.
+
+ABI and ABI extensions
+^^^^^^^^^^^^^^^^^^^^^^
+
+There has also been considerable ABI work since the 3.4 release. This release
+adds support for the N32 ABI, the O32-FPXX ABI Extension, the O32-FP64 ABI
+Extension, and the O32-FP64A ABI Extension.
+
+The N32 ABI is an existing ABI that has now been implemented in LLVM. It is a
+64-bit ABI that is similar to N64 but retains 32-bit pointers. N64 remains the
+default 64-bit ABI in LLVM. This differs from GCC where N32 is the default
+64-bit ABI.
+
+The O32-FPXX ABI Extension is 100% compatible with the O32-ABI and the O32-FP64
+ABI Extension and may be linked with either but may not be linked with both of
+these simultaneously. It extends the O32 ABI to allow the same code to execute
+without modification on processors with 32-bit FPU registers as well as 64-bit
+FPU registers. The O32-FPXX ABI Extension is enabled by default for the O32 ABI
+on mips*-img-linux-gnu and mips*-mti-linux-gnu triples and is selected with
+-mfpxx. It is expected that future releases of LLVM will enable the FPXX
+Extension for O32 on all triples.
+
+The O32-FP64 ABI Extension is an extension to the O32 ABI to fully exploit FPU's
+with 64-bit registers and is enabled with -mfp64. This replaces an undocumented
+and unsupported O32 extension which was previously enabled with -mfp64. It is
+100% compatible with the O32-FPXX ABI Extension.
+
+The O32-FP64A ABI Extension is a restricted form of the O32-FP64 ABI Extension
+which allows interlinking with unmodified binaries that use the base O32 ABI.
+
+Integrated Assembler
+^^^^^^^^^^^^^^^^^^^^
+
+The MIPS Integrated Assembler has undergone a substantial overhaul including a
+rewrite of the assembly parser. It's not ready for general use in this release
+but adventurous users may wish to enable it using ``-fintegrated-as``.
+
+In this release, the integrated assembler supports the majority of MIPS-I,
+MIPS-II, MIPS-III, MIPS-IV, MIPS-V, MIPS32, MIPS32r2, MIPS32r6, MIPS64,
+MIPS64r2, and MIPS64r6 as well as some of the Application Specific Extensions
+such as MSA. It also supports several of the MIPS specific assembler directives
+such as ``.set``, ``.module``, ``.cpload``, etc.
+
+External Open Source Projects Using LLVM 3.5
+============================================
+
+An exciting aspect of LLVM is that it is used as an enabling technology for
+a lot of other language and tools projects. This section lists some of the
+projects that have already been updated to work with LLVM 3.5.