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R600/SI: Add other LDS atomic operations
[oota-llvm.git]
/
CREDITS.TXT
diff --git
a/CREDITS.TXT
b/CREDITS.TXT
index f468cd5ce4ff617398f8c638ad15202bbb16cd2a..0447c40e381b547a2e2e7db3723213ce8085cfd7 100644
(file)
--- a/
CREDITS.TXT
+++ b/
CREDITS.TXT
@@
-5,8
+5,8
@@
done!
The list is sorted by surname and formatted to allow easy grepping and
beautification by scripts. The fields are: name (N), email (E), web-address
The list is sorted by surname and formatted to allow easy grepping and
beautification by scripts. The fields are: name (N), email (E), web-address
-(W), PGP key ID and fingerprint (P), description (D),
and
snail-mail address
-(S).
+(W), PGP key ID and fingerprint (P), description (D), snail-mail address
+(S)
, and (I) IRC handle
.
N: Vikram Adve
N: Vikram Adve
@@
-17,11
+17,15
@@
D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
N: Owen Anderson
E: resistor@mac.com
D: LCSSA pass and related LoopUnswitch work
N: Owen Anderson
E: resistor@mac.com
D: LCSSA pass and related LoopUnswitch work
-D: GVNPRE pass,
TargetData
refactoring, random improvements
+D: GVNPRE pass,
DataLayout
refactoring, random improvements
N: Henrik Bach
D: MingW Win32 API portability layer
N: Henrik Bach
D: MingW Win32 API portability layer
+N: Aaron Ballman
+E: aaron@aaronballman.com
+D: __declspec attributes, Windows support, general bug fixing
+
N: Nate Begeman
E: natebegeman@mac.com
D: PowerPC backend developer
N: Nate Begeman
E: natebegeman@mac.com
D: PowerPC backend developer
@@
-50,9
+54,17
@@
N: Cameron Buschardt
E: buschard@uiuc.edu
D: The `mem2reg' pass - promotes values stored in memory to registers
E: buschard@uiuc.edu
D: The `mem2reg' pass - promotes values stored in memory to registers
+N: Brendon Cahoon
+E: bcahoon@codeaurora.org
+D: Loop unrolling with run-time trip counts.
+
N: Chandler Carruth
E: chandlerc@gmail.com
N: Chandler Carruth
E: chandlerc@gmail.com
-D: LinkTimeOptimizer for Linux, via binutils integration, and C API
+E: chandlerc@google.com
+D: Hashing algorithms and interfaces
+D: Inline cost analysis
+D: Machine block placement pass
+D: SROA
N: Casey Carter
E: ccarter@uiuc.edu
N: Casey Carter
E: ccarter@uiuc.edu
@@
-83,14
+95,22
@@
N: John T. Criswell
E: criswell@uiuc.edu
D: Original Autoconf support, documentation improvements, bug fixes
E: criswell@uiuc.edu
D: Original Autoconf support, documentation improvements, bug fixes
+N: Anshuman Dasgupta
+E: adasgupt@codeaurora.org
+D: Deterministic finite automaton based infrastructure for VLIW packetization
+
N: Stefanus Du Toit
N: Stefanus Du Toit
-E: stefanus.du
toit@rapidmind
.com
+E: stefanus.du
.toit@intel
.com
D: Bug fixes and minor improvements
N: Rafael Avila de Espindola
E: rafael.espindola@gmail.com
D: The ARM backend
D: Bug fixes and minor improvements
N: Rafael Avila de Espindola
E: rafael.espindola@gmail.com
D: The ARM backend
+N: Dave Estes
+E: cestes@codeaurora.org
+D: AArch64 machine description for Cortex-A53
+
N: Alkis Evlogimenos
E: alkis@evlogimenos.com
D: Linear scan register allocator, many codegen improvements, Java frontend
N: Alkis Evlogimenos
E: alkis@evlogimenos.com
D: Linear scan register allocator, many codegen improvements, Java frontend
@@
-116,6
+136,7
@@
W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
D: PPC backend fixes for Linux
N: Louis Gerbarg
D: PPC backend fixes for Linux
N: Louis Gerbarg
+E: lgg@apple.com
D: Portions of the PowerPC backend
N: Saem Ghani
D: Portions of the PowerPC backend
N: Saem Ghani
@@
-127,7
+148,7
@@
E: foldr@codedgers.com
D: Author of llvmc2
N: Dan Gohman
D: Author of llvmc2
N: Dan Gohman
-E:
gohman@apple
.com
+E:
dan433584@gmail
.com
D: Miscellaneous bug fixes
N: David Goodwin
D: Miscellaneous bug fixes
N: David Goodwin
@@
-145,10
+166,12
@@
D: Improvements for space efficiency
N: James Grosbach
E: grosbach@apple.com
N: James Grosbach
E: grosbach@apple.com
+I: grosbach
D: SjLj exception handling support
D: General fixes and improvements for the ARM back-end
D: MCJIT
D: ARM integrated assembler and assembly parser
D: SjLj exception handling support
D: General fixes and improvements for the ARM back-end
D: MCJIT
D: ARM integrated assembler and assembly parser
+D: Led effort for the backend formerly known as ARM64
N: Lang Hames
E: lhames@gmail.com
N: Lang Hames
E: lhames@gmail.com
@@
-206,6
+229,10
@@
N: Benjamin Kramer
E: benny.kra@gmail.com
D: Miscellaneous bug fixes
E: benny.kra@gmail.com
D: Miscellaneous bug fixes
+N: Sundeep Kushwaha
+E: sundeepk@codeaurora.org
+D: Implemented DFA-based target independent VLIW packetizer
+
N: Christopher Lamb
E: christopher.lamb@gmail.com
D: aligned load/store support, parts of noalias and restrict support
N: Christopher Lamb
E: christopher.lamb@gmail.com
D: aligned load/store support, parts of noalias and restrict support
@@
-231,6
+258,13
@@
D: The initial llvm-ar tool, converted regression testsuite to dejagnu
D: Modulo scheduling in the SparcV9 backend
D: Release manager (1.7+)
D: Modulo scheduling in the SparcV9 backend
D: Release manager (1.7+)
+N: Sylvestre Ledru
+E: sylvestre@debian.org
+W: http://sylvestre.ledru.info/
+W: http://llvm.org/apt/
+D: Debian and Ubuntu packaging
+D: Continuous integration with jenkins
+
N: Andrew Lenharth
E: alenhar2@cs.uiuc.edu
W: http://www.lenharth.org/~andrewl/
N: Andrew Lenharth
E: alenhar2@cs.uiuc.edu
W: http://www.lenharth.org/~andrewl/
@@
-241,6
+275,10
@@
N: Nick Lewycky
E: nicholas@mxc.ca
D: PredicateSimplifier pass
E: nicholas@mxc.ca
D: PredicateSimplifier pass
+N: Tony Linthicum, et. al.
+E: tlinth@codeaurora.org
+D: Backend for Qualcomm's Hexagon VLIW processor.
+
N: Bruno Cardoso Lopes
E: bruno.cardoso@gmail.com
W: http://www.brunocardoso.org
N: Bruno Cardoso Lopes
E: bruno.cardoso@gmail.com
W: http://www.brunocardoso.org
@@
-267,6
+305,11
@@
N: Scott Michel
E: scottm@aero.org
D: Added STI Cell SPU backend.
E: scottm@aero.org
D: Added STI Cell SPU backend.
+N: Kai Nacke
+E: kai@redstar.de
+D: Support for implicit TLS model used with MS VC runtime
+D: Dumping of Win64 EH structures
+
N: Takumi Nakamura
E: geek4civic@gmail.com
E: chapuni@hf.rim.or.jp
N: Takumi Nakamura
E: geek4civic@gmail.com
E: chapuni@hf.rim.or.jp
@@
-302,9
+345,9
@@
D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
D: Optimizer improvements, Loop Index Split
D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
D: Optimizer improvements, Loop Index Split
-N:
Sandeep Patel
-E:
deeppatel1987@gmail.com
-D:
ARM calling conventions rewrite, hard float support
+N:
Ana Pazos
+E:
apazos@codeaurora.org
+D:
Fixes and improvements to the AArch64 backend
N: Wesley Peck
E: peckw@wesleypeck.com
N: Wesley Peck
E: peckw@wesleypeck.com
@@
-320,18
+363,29
@@
W: http://vladimir_prus.blogspot.com
E: ghost@cs.msu.su
D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
E: ghost@cs.msu.su
D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
+N: Kalle Raiskila
+E: kalle.rasikila@nokia.com
+D: Some bugfixes to CellSPU
+
N: Xerxes Ranby
E: xerxes@zafena.se
D: Cmake dependency chain and various bug fixes
N: Xerxes Ranby
E: xerxes@zafena.se
D: Cmake dependency chain and various bug fixes
+N: Alex Rosenberg
+E: alexr@leftfield.org
+I: arosenberg
+D: ARM calling conventions rewrite, hard float support
+
N: Chad Rosier
N: Chad Rosier
-E: mcrosier@apple.com
-D: ARM fast-isel improvements
-D: Performance monitoring
+E: mcrosier@codeaurora.org
+I: mcrosier
+D: AArch64 fast instruction selection pass
+D: Fixes and improvements to the ARM fast-isel pass
+D: Fixes and improvements to the AArch64 backend
N: Nadav Rotem
N: Nadav Rotem
-E: n
adav.rotem@intel
.com
-D:
Vector code generation improvements
.
+E: n
rotem@apple
.com
+D:
X86 code generation improvements, Loop Vectorizer
.
N: Roman Samoilov
E: roman@codedgers.com
N: Roman Samoilov
E: roman@codedgers.com
@@
-339,6
+393,7
@@
D: MSIL backend
N: Duncan Sands
E: baldrick@free.fr
N: Duncan Sands
E: baldrick@free.fr
+I: baldrick
D: Ada support in llvm-gcc
D: Dragonegg plugin
D: Exception handling improvements
D: Ada support in llvm-gcc
D: Dragonegg plugin
D: Exception handling improvements
@@
-370,6
+425,15
@@
E: rspencer@reidspencer.com
W: http://reidspencer.com/
D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
W: http://reidspencer.com/
D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
+N: Alp Toker
+E: alp@nuanti.com
+W: http://atoker.com/
+D: C++ frontend next generation standards implementation
+
+N: Craig Topper
+E: craig.topper@gmail.com
+D: X86 codegen and disassembler improvements. AVX2 support.
+
N: Edwin Torok
E: edwintorok@gmail.com
D: Miscellaneous bug fixes
N: Edwin Torok
E: edwintorok@gmail.com
D: Miscellaneous bug fixes
@@
-384,10
+448,11
@@
D: ARM backend improvements
D: Thread Local Storage implementation
N: Bill Wendling
D: Thread Local Storage implementation
N: Bill Wendling
-E: wendling@apple.com
-D: Exception handling
+I: wendling
+E: isanbard@gmail.com
+D: Release manager, IR Linker, LTO
D: Bunches of stuff
N: Bob Wilson
E: bob.wilson@acm.org
D: Bunches of stuff
N: Bob Wilson
E: bob.wilson@acm.org
-D: Advanced SIMD (NEON) support in the ARM backend
+D: Advanced SIMD (NEON) support in the ARM backend
.