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[PowerPC] Add predicted forms of branches
[oota-llvm.git]
/
CODE_OWNERS.TXT
diff --git
a/CODE_OWNERS.TXT
b/CODE_OWNERS.TXT
index ac74e1e36e3517f0214eef1a94149d41312ab20b..8e13e35f403332efd5040f79c16eddf61ea898a1 100644
(file)
--- a/
CODE_OWNERS.TXT
+++ b/
CODE_OWNERS.TXT
@@
-16,10
+16,14
@@
N: Owen Anderson
E: resistor@mac.com
D: SelectionDAG (lib/CodeGen/SelectionDAG/*)
E: resistor@mac.com
D: SelectionDAG (lib/CodeGen/SelectionDAG/*)
+N: Rafael Avila de Espindola
+E: rafael.espindola@gmail.com
+D: Gold plugin (tools/gold/*)
+
N: Chandler Carruth
E: chandlerc@gmail.com
E: chandlerc@google.com
N: Chandler Carruth
E: chandlerc@gmail.com
E: chandlerc@google.com
-D: Config, ADT, Support, inlining & related pass
se
, SROA/mem2reg & related passes, CMake, library layering
+D: Config, ADT, Support, inlining & related pass
es
, SROA/mem2reg & related passes, CMake, library layering
N: Evan Cheng
E: evan.cheng@apple.com
N: Evan Cheng
E: evan.cheng@apple.com
@@
-35,12
+39,17
@@
D: LLDB
N: Peter Collingbourne
D: libclc
N: Peter Collingbourne
D: libclc
+N: Anshuman Dasgupta
+E: adasgupt@codeaurora.org
+D: Hexagon Backend
+
N: Hal Finkel
E: hfinkel@anl.gov
D: BBVectorize and the PowerPC target
N: Hal Finkel
E: hfinkel@anl.gov
D: BBVectorize and the PowerPC target
-N: Doug Gregor
-D: Clang Frontend Libraries
+N: Venkatraman Govindaraju
+E: venkatra@cs.wisc.edu
+D: Sparc Backend (lib/Target/Sparc/*)
N: Tobias Grosser
D: Polly
N: Tobias Grosser
D: Polly
@@
-56,6
+65,10
@@
N: Justin Holewinski
E: jholewinski@nvidia.com
D: NVPTX Target (lib/Target/NVPTX/*)
E: jholewinski@nvidia.com
D: NVPTX Target (lib/Target/NVPTX/*)
+N: Andy Kaylor
+E: andrew.kaylor@intel.com
+D: MCJIT, RuntimeDyld and JIT event listeners
+
N: Galina Kistanova
E: gkistanova@gmail.com
D: LLVM Buildbot
N: Galina Kistanova
E: gkistanova@gmail.com
D: LLVM Buildbot
@@
-68,9
+81,6
@@
N: Benjamin Kramer
E: benny.kra@gmail.com
D: DWARF Parser
E: benny.kra@gmail.com
D: DWARF Parser
-N: Ted Kremenek
-D: Clang Static Analyzer
-
N: Sergei Larin
E: slarin@codeaurora.org
D: VLIW Instruction Scheduling, Packetization
N: Sergei Larin
E: slarin@codeaurora.org
D: VLIW Instruction Scheduling, Packetization
@@
-80,25
+90,46
@@
E: sabre@nondot.org
W: http://nondot.org/~sabre/
D: Everything not covered by someone else
W: http://nondot.org/~sabre/
D: Everything not covered by someone else
-N:
John McCall
-E:
rjmccall@apple
.com
-D:
Clang LLVM IR generation
+N:
Tim Northover
+E:
Tim.Northover@arm
.com
+D:
AArch64 backend
N: Jakob Olesen
D: Register allocators and TableGen
N: Jakob Olesen
D: Register allocators and TableGen
+N: Richard Osborne
+E: richard@xmos.com
+D: XCore Backend
+
N: Chad Rosier
E: mcrosier@apple.com
N: Chad Rosier
E: mcrosier@apple.com
-D:
MS-inline asm, fast-i
sel
+D:
Fast-I
sel
N: Nadav Rotem
E: nrotem@apple.com
D: X86 Backend, Loop Vectorizer
N: Nadav Rotem
E: nrotem@apple.com
D: X86 Backend, Loop Vectorizer
+N: Richard Sandiford
+E: rsandifo@linux.vnet.ibm.com
+D: SystemZ Backend
+
N: Duncan Sands
E: baldrick@free.fr
D: DragonEgg
N: Duncan Sands
E: baldrick@free.fr
D: DragonEgg
+N: Michael Spencer
+E: bigcheesegs@gmail.com
+D: Windows parts of Support, Object, ar, nm, objdump, ranlib, size
+
+N: Tom Stellard
+E: thomas.stellard@amd.com
+E: mesa-dev@lists.freedesktop.org
+D: R600 Backend
+
N: Andrew Trick
E: atrick@apple.com
N: Andrew Trick
E: atrick@apple.com
-D: Instruction Scheduling
+D: IndVar Simplify, Loop Strength Reduction, Instruction Scheduling
+
+N: Bill Wendling
+E: wendling@apple.com
+D: libLTO, IR Linker