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Remove default in fully-covered switch (to fix Clang -Werror -Wcovered-switch-default)
[oota-llvm.git]
/
CODE_OWNERS.TXT
diff --git
a/CODE_OWNERS.TXT
b/CODE_OWNERS.TXT
index 544e6d9005bde2b03481fb6cec6a1917b4687950..4e8ff888929e63973a2c21f4da5f1064534d045e 100644
(file)
--- a/
CODE_OWNERS.TXT
+++ b/
CODE_OWNERS.TXT
@@
-33,10
+33,6
@@
N: Evan Cheng
E: evan.cheng@apple.com
D: ARM target, parts of code generator not covered by someone else
E: evan.cheng@apple.com
D: ARM target, parts of code generator not covered by someone else
-N: Renato Golin
-E: renato.golin@linaro.org
-D: ARM Linux support
-
N: Eric Christopher
E: echristo@gmail.com
D: Debug Information, autotools/configure/make build, inline assembly
N: Eric Christopher
E: echristo@gmail.com
D: Debug Information, autotools/configure/make build, inline assembly
@@
-51,16
+47,28
@@
D: libc++
N: Peter Collingbourne
E: peter@pcc.me.uk
N: Peter Collingbourne
E: peter@pcc.me.uk
-D: libclc, llgo
+D: llgo
+
+N: Quentin Colombet
+E: qcolombet@apple.com
+D: Register allocators
N: Anshuman Dasgupta
E: adasgupt@codeaurora.org
D: Hexagon Backend
N: Anshuman Dasgupta
E: adasgupt@codeaurora.org
D: Hexagon Backend
+N: Duncan P. N. Exon Smith
+E: dexonsmith@apple.com
+D: Branch weights and BlockFrequencyInfo
+
N: Hal Finkel
E: hfinkel@anl.gov
D: BBVectorize, the loop reroller, alias analysis and the PowerPC target
N: Hal Finkel
E: hfinkel@anl.gov
D: BBVectorize, the loop reroller, alias analysis and the PowerPC target
+N: Renato Golin
+E: renato.golin@linaro.org
+D: ARM Linux support
+
N: Venkatraman Govindaraju
E: venkatra@cs.wisc.edu
D: Sparc Backend (lib/Target/Sparc/*)
N: Venkatraman Govindaraju
E: venkatra@cs.wisc.edu
D: Sparc Backend (lib/Target/Sparc/*)
@@
-73,10
+81,6
@@
N: James Grosbach
E: grosbach@apple.com
D: MC layer
E: grosbach@apple.com
D: MC layer
-N: Duncan P. N. Exon Smith
-E: dexonsmith@apple.com
-D: Branch weights and BlockFrequencyInfo
-
N: Justin Holewinski
E: jholewinski@nvidia.com
D: NVPTX Target (lib/Target/NVPTX/*)
N: Justin Holewinski
E: jholewinski@nvidia.com
D: NVPTX Target (lib/Target/NVPTX/*)
@@
-116,7
+120,7
@@
D: SampleProfile and related parts of ProfileData
N: Jakob Olesen
E: stoklund@2pi.dk
N: Jakob Olesen
E: stoklund@2pi.dk
-D:
Register allocators and
TableGen
+D: TableGen
N: Richard Osborne
E: richard@xmos.com
N: Richard Osborne
E: richard@xmos.com
@@
-126,6
+130,10
@@
N: Chad Rosier
E: mcrosier@codeaurora.org
D: Fast-Isel
E: mcrosier@codeaurora.org
D: Fast-Isel
+N: Alex Rosenberg
+E: alexr@leftfield.org
+D: Sony PlayStation®4 support
+
N: Nadav Rotem
E: nrotem@apple.com
D: X86 Backend, Loop Vectorizer
N: Nadav Rotem
E: nrotem@apple.com
D: X86 Backend, Loop Vectorizer
@@
-134,10
+142,6
@@
N: Daniel Sanders
E: daniel.sanders@imgtec.com
D: MIPS Backend (lib/Target/Mips/*)
E: daniel.sanders@imgtec.com
D: MIPS Backend (lib/Target/Mips/*)
-N: Richard Sandiford
-E: rsandifo@linux.vnet.ibm.com
-D: SystemZ Backend
-
N: Duncan Sands
E: baldrick@free.fr
D: DragonEgg
N: Duncan Sands
E: baldrick@free.fr
D: DragonEgg
@@
-150,10
+154,14
@@
N: Michael Spencer
E: bigcheesegs@gmail.com
D: Windows parts of Support, Object, ar, nm, objdump, ranlib, size
E: bigcheesegs@gmail.com
D: Windows parts of Support, Object, ar, nm, objdump, ranlib, size
+N: Alexei Starovoitov
+E: alexei.starovoitov@gmail.com
+D: BPF backend
+
N: Tom Stellard
E: thomas.stellard@amd.com
E: mesa-dev@lists.freedesktop.org
N: Tom Stellard
E: thomas.stellard@amd.com
E: mesa-dev@lists.freedesktop.org
-D: Release manager for the 3.5
branch, R600 Backend
+D: Release manager for the 3.5
and 3.6 branches, R600 Backend, libclc
N: Evgeniy Stepanov
E: eugenis@google.com
N: Evgeniy Stepanov
E: eugenis@google.com
@@
-163,6
+171,10
@@
N: Andrew Trick
E: atrick@apple.com
D: IndVar Simplify, Loop Strength Reduction, Instruction Scheduling
E: atrick@apple.com
D: IndVar Simplify, Loop Strength Reduction, Instruction Scheduling
+N: Ulrich Weigand
+E: uweigand@de.ibm.com
+D: SystemZ Backend
+
N: Bill Wendling
E: isanbard@gmail.com
D: libLTO, IR Linker
N: Bill Wendling
E: isanbard@gmail.com
D: libLTO, IR Linker