1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
63 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
64 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
65 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
66 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22, PD = 23, T8PD = 24, TAPD = 25
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
234 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
235 HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
248 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
249 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
250 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
251 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
253 Name = Rec->getName();
254 AsmString = Rec->getValueAsString("AsmString");
256 Operands = &insn.Operands.OperandList;
258 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
260 // Check for 64-bit inst which does not require REX
263 // FIXME: Is there some better way to check for In64BitMode?
264 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
265 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
266 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
267 Predicates[i]->getName().find("In32Bit") != Name.npos) {
271 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
277 ShouldBeEmitted = true;
280 void RecognizableInstr::processInstr(DisassemblerTables &tables,
281 const CodeGenInstruction &insn,
284 // Ignore "asm parser only" instructions.
285 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
288 RecognizableInstr recogInstr(tables, insn, uid);
290 recogInstr.emitInstructionSpecifier();
292 if (recogInstr.shouldBeEmitted())
293 recogInstr.emitDecodePath(tables);
296 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
297 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
298 (HasEVEX_KZ ? n##_KZ : \
299 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
301 InstructionContext RecognizableInstr::insnContext() const {
302 InstructionContext insnContext;
305 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
306 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
307 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
310 if (HasVEX_LPrefix && HasVEX_WPrefix) {
311 if (HasOpSizePrefix || Prefix == X86Local::PD)
312 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
313 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
314 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
315 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
316 Prefix == X86Local::TAXD)
317 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
319 insnContext = EVEX_KB(IC_EVEX_L_W);
320 } else if (HasVEX_LPrefix) {
322 if (HasOpSizePrefix || Prefix == X86Local::PD ||
323 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
324 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
325 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
326 insnContext = EVEX_KB(IC_EVEX_L_XS);
327 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
328 Prefix == X86Local::TAXD)
329 insnContext = EVEX_KB(IC_EVEX_L_XD);
331 insnContext = EVEX_KB(IC_EVEX_L);
333 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
335 if (HasOpSizePrefix || Prefix == X86Local::PD ||
336 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
337 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
338 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
339 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
340 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
341 Prefix == X86Local::TAXD)
342 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
344 insnContext = EVEX_KB(IC_EVEX_L2_W);
345 } else if (HasEVEX_L2Prefix) {
347 if (HasOpSizePrefix || Prefix == X86Local::PD ||
348 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
349 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
350 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
351 Prefix == X86Local::TAXD)
352 insnContext = EVEX_KB(IC_EVEX_L2_XD);
353 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
354 insnContext = EVEX_KB(IC_EVEX_L2_XS);
356 insnContext = EVEX_KB(IC_EVEX_L2);
358 else if (HasVEX_WPrefix) {
360 if (HasOpSizePrefix || Prefix == X86Local::PD ||
361 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
362 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
363 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
364 insnContext = EVEX_KB(IC_EVEX_W_XS);
365 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
366 Prefix == X86Local::TAXD)
367 insnContext = EVEX_KB(IC_EVEX_W_XD);
369 insnContext = EVEX_KB(IC_EVEX_W);
372 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
373 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
374 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
375 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
376 Prefix == X86Local::TAXD)
377 insnContext = EVEX_KB(IC_EVEX_XD);
378 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
379 insnContext = EVEX_KB(IC_EVEX_XS);
381 insnContext = EVEX_KB(IC_EVEX);
383 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
384 if (HasVEX_LPrefix && HasVEX_WPrefix) {
385 if (HasOpSizePrefix || Prefix == X86Local::PD ||
386 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
387 insnContext = IC_VEX_L_W_OPSIZE;
388 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
389 insnContext = IC_VEX_L_W_XS;
390 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
391 Prefix == X86Local::TAXD)
392 insnContext = IC_VEX_L_W_XD;
394 insnContext = IC_VEX_L_W;
395 } else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
396 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
398 insnContext = IC_VEX_L_OPSIZE;
399 else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
400 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
402 insnContext = IC_VEX_W_OPSIZE;
403 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
404 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
405 insnContext = IC_VEX_OPSIZE;
406 else if (HasVEX_LPrefix &&
407 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
408 insnContext = IC_VEX_L_XS;
409 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
410 Prefix == X86Local::T8XD ||
411 Prefix == X86Local::TAXD))
412 insnContext = IC_VEX_L_XD;
413 else if (HasVEX_WPrefix &&
414 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
415 insnContext = IC_VEX_W_XS;
416 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
417 Prefix == X86Local::T8XD ||
418 Prefix == X86Local::TAXD))
419 insnContext = IC_VEX_W_XD;
420 else if (HasVEX_WPrefix)
421 insnContext = IC_VEX_W;
422 else if (HasVEX_LPrefix)
423 insnContext = IC_VEX_L;
424 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
425 Prefix == X86Local::TAXD)
426 insnContext = IC_VEX_XD;
427 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
428 insnContext = IC_VEX_XS;
430 insnContext = IC_VEX;
431 } else if (Is64Bit || HasREX_WPrefix) {
432 if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD ||
433 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD))
434 insnContext = IC_64BIT_REXW_OPSIZE;
435 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
436 Prefix == X86Local::T8XD ||
437 Prefix == X86Local::TAXD))
438 insnContext = IC_64BIT_XD_OPSIZE;
439 else if (HasOpSizePrefix &&
440 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
441 insnContext = IC_64BIT_XS_OPSIZE;
442 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
443 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
444 insnContext = IC_64BIT_OPSIZE;
445 else if (HasAdSizePrefix)
446 insnContext = IC_64BIT_ADSIZE;
447 else if (HasREX_WPrefix &&
448 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
449 insnContext = IC_64BIT_REXW_XS;
450 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
451 Prefix == X86Local::T8XD ||
452 Prefix == X86Local::TAXD))
453 insnContext = IC_64BIT_REXW_XD;
454 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
455 Prefix == X86Local::TAXD)
456 insnContext = IC_64BIT_XD;
457 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
458 insnContext = IC_64BIT_XS;
459 else if (HasREX_WPrefix)
460 insnContext = IC_64BIT_REXW;
462 insnContext = IC_64BIT;
464 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
465 Prefix == X86Local::T8XD ||
466 Prefix == X86Local::TAXD))
467 insnContext = IC_XD_OPSIZE;
468 else if (HasOpSizePrefix &&
469 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
470 insnContext = IC_XS_OPSIZE;
471 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
472 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
473 insnContext = IC_OPSIZE;
474 else if (HasAdSizePrefix)
475 insnContext = IC_ADSIZE;
476 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
477 Prefix == X86Local::TAXD)
479 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
480 Prefix == X86Local::REP)
489 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
494 // Filter out intrinsics
496 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
498 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
499 return FILTER_STRONG;
502 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
503 // printed as a separate "instruction".
511 // Filter out instructions with a LOCK prefix;
512 // prefer forms that do not have the prefix
518 if (Name == "VMASKMOVDQU64")
521 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
522 // For now, just prefer the REP versions.
523 if (Name == "XACQUIRE_PREFIX" ||
524 Name == "XRELEASE_PREFIX")
527 return FILTER_NORMAL;
530 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
531 unsigned &physicalOperandIndex,
532 unsigned &numPhysicalOperands,
533 const unsigned *operandMapping,
534 OperandEncoding (*encodingFromString)
536 bool hasOpSizePrefix)) {
538 if (physicalOperandIndex >= numPhysicalOperands)
541 assert(physicalOperandIndex < numPhysicalOperands);
544 while (operandMapping[operandIndex] != operandIndex) {
545 Spec->operands[operandIndex].encoding = ENCODING_DUP;
546 Spec->operands[operandIndex].type =
547 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
551 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
553 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
555 Spec->operands[operandIndex].type = typeFromString(typeName,
561 ++physicalOperandIndex;
564 void RecognizableInstr::emitInstructionSpecifier() {
567 if (!ShouldBeEmitted)
572 Spec->filtered = true;
575 ShouldBeEmitted = false;
581 Spec->insnContext = insnContext();
583 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
585 unsigned numOperands = OperandList.size();
586 unsigned numPhysicalOperands = 0;
588 // operandMapping maps from operands in OperandList to their originals.
589 // If operandMapping[i] != i, then the entry is a duplicate.
590 unsigned operandMapping[X86_MAX_OPERANDS];
591 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
593 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
594 if (OperandList[operandIndex].Constraints.size()) {
595 const CGIOperandList::ConstraintInfo &Constraint =
596 OperandList[operandIndex].Constraints[0];
597 if (Constraint.isTied()) {
598 operandMapping[operandIndex] = operandIndex;
599 operandMapping[Constraint.getTiedOperand()] = operandIndex;
601 ++numPhysicalOperands;
602 operandMapping[operandIndex] = operandIndex;
605 ++numPhysicalOperands;
606 operandMapping[operandIndex] = operandIndex;
610 #define HANDLE_OPERAND(class) \
611 handleOperand(false, \
613 physicalOperandIndex, \
614 numPhysicalOperands, \
616 class##EncodingFromString);
618 #define HANDLE_OPTIONAL(class) \
619 handleOperand(true, \
621 physicalOperandIndex, \
622 numPhysicalOperands, \
624 class##EncodingFromString);
626 // operandIndex should always be < numOperands
627 unsigned operandIndex = 0;
628 // physicalOperandIndex should always be < numPhysicalOperands
629 unsigned physicalOperandIndex = 0;
632 default: llvm_unreachable("Unhandled form");
633 case X86Local::RawFrm:
634 // Operand 1 (optional) is an address or immediate.
635 // Operand 2 (optional) is an immediate.
636 assert(numPhysicalOperands <= 2 &&
637 "Unexpected number of operands for RawFrm");
638 HANDLE_OPTIONAL(relocation)
639 HANDLE_OPTIONAL(immediate)
641 case X86Local::RawFrmMemOffs:
642 // Operand 1 is an address.
643 HANDLE_OPERAND(relocation);
645 case X86Local::AddRegFrm:
646 // Operand 1 is added to the opcode.
647 // Operand 2 (optional) is an address.
648 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
649 "Unexpected number of operands for AddRegFrm");
650 HANDLE_OPERAND(opcodeModifier)
651 HANDLE_OPTIONAL(relocation)
653 case X86Local::MRMDestReg:
654 // Operand 1 is a register operand in the R/M field.
655 // Operand 2 is a register operand in the Reg/Opcode field.
656 // - In AVX, there is a register operand in the VEX.vvvv field here -
657 // Operand 3 (optional) is an immediate.
659 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
660 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
662 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
663 "Unexpected number of operands for MRMDestRegFrm");
665 HANDLE_OPERAND(rmRegister)
668 // FIXME: In AVX, the register below becomes the one encoded
669 // in ModRMVEX and the one above the one in the VEX.VVVV field
670 HANDLE_OPERAND(vvvvRegister)
672 HANDLE_OPERAND(roRegister)
673 HANDLE_OPTIONAL(immediate)
675 case X86Local::MRMDestMem:
676 // Operand 1 is a memory operand (possibly SIB-extended)
677 // Operand 2 is a register operand in the Reg/Opcode field.
678 // - In AVX, there is a register operand in the VEX.vvvv field here -
679 // Operand 3 (optional) is an immediate.
681 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
682 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
684 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
685 "Unexpected number of operands for MRMDestMemFrm");
686 HANDLE_OPERAND(memory)
689 HANDLE_OPERAND(writemaskRegister)
692 // FIXME: In AVX, the register below becomes the one encoded
693 // in ModRMVEX and the one above the one in the VEX.VVVV field
694 HANDLE_OPERAND(vvvvRegister)
696 HANDLE_OPERAND(roRegister)
697 HANDLE_OPTIONAL(immediate)
699 case X86Local::MRMSrcReg:
700 // Operand 1 is a register operand in the Reg/Opcode field.
701 // Operand 2 is a register operand in the R/M field.
702 // - In AVX, there is a register operand in the VEX.vvvv field here -
703 // Operand 3 (optional) is an immediate.
704 // Operand 4 (optional) is an immediate.
706 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
707 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
708 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
710 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
711 "Unexpected number of operands for MRMSrcRegFrm");
713 HANDLE_OPERAND(roRegister)
716 HANDLE_OPERAND(writemaskRegister)
719 // FIXME: In AVX, the register below becomes the one encoded
720 // in ModRMVEX and the one above the one in the VEX.VVVV field
721 HANDLE_OPERAND(vvvvRegister)
724 HANDLE_OPERAND(immediate)
726 HANDLE_OPERAND(rmRegister)
728 if (HasVEX_4VOp3Prefix)
729 HANDLE_OPERAND(vvvvRegister)
731 if (!HasMemOp4Prefix)
732 HANDLE_OPTIONAL(immediate)
733 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
734 HANDLE_OPTIONAL(immediate)
736 case X86Local::MRMSrcMem:
737 // Operand 1 is a register operand in the Reg/Opcode field.
738 // Operand 2 is a memory operand (possibly SIB-extended)
739 // - In AVX, there is a register operand in the VEX.vvvv field here -
740 // Operand 3 (optional) is an immediate.
742 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
743 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
744 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
746 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
747 "Unexpected number of operands for MRMSrcMemFrm");
749 HANDLE_OPERAND(roRegister)
752 HANDLE_OPERAND(writemaskRegister)
755 // FIXME: In AVX, the register below becomes the one encoded
756 // in ModRMVEX and the one above the one in the VEX.VVVV field
757 HANDLE_OPERAND(vvvvRegister)
760 HANDLE_OPERAND(immediate)
762 HANDLE_OPERAND(memory)
764 if (HasVEX_4VOp3Prefix)
765 HANDLE_OPERAND(vvvvRegister)
767 if (!HasMemOp4Prefix)
768 HANDLE_OPTIONAL(immediate)
769 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
771 case X86Local::MRM0r:
772 case X86Local::MRM1r:
773 case X86Local::MRM2r:
774 case X86Local::MRM3r:
775 case X86Local::MRM4r:
776 case X86Local::MRM5r:
777 case X86Local::MRM6r:
778 case X86Local::MRM7r:
780 // Operand 1 is a register operand in the R/M field.
781 // Operand 2 (optional) is an immediate or relocation.
782 // Operand 3 (optional) is an immediate.
783 unsigned kOp = (HasEVEX_K) ? 1:0;
784 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
785 if (numPhysicalOperands > 3 + kOp + Op4v)
786 llvm_unreachable("Unexpected number of operands for MRMnr");
789 HANDLE_OPERAND(vvvvRegister)
792 HANDLE_OPERAND(writemaskRegister)
793 HANDLE_OPTIONAL(rmRegister)
794 HANDLE_OPTIONAL(relocation)
795 HANDLE_OPTIONAL(immediate)
797 case X86Local::MRM0m:
798 case X86Local::MRM1m:
799 case X86Local::MRM2m:
800 case X86Local::MRM3m:
801 case X86Local::MRM4m:
802 case X86Local::MRM5m:
803 case X86Local::MRM6m:
804 case X86Local::MRM7m:
806 // Operand 1 is a memory operand (possibly SIB-extended)
807 // Operand 2 (optional) is an immediate or relocation.
808 unsigned kOp = (HasEVEX_K) ? 1:0;
809 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
810 if (numPhysicalOperands < 1 + kOp + Op4v ||
811 numPhysicalOperands > 2 + kOp + Op4v)
812 llvm_unreachable("Unexpected number of operands for MRMnm");
815 HANDLE_OPERAND(vvvvRegister)
817 HANDLE_OPERAND(writemaskRegister)
818 HANDLE_OPERAND(memory)
819 HANDLE_OPTIONAL(relocation)
821 case X86Local::RawFrmImm8:
822 // operand 1 is a 16-bit immediate
823 // operand 2 is an 8-bit immediate
824 assert(numPhysicalOperands == 2 &&
825 "Unexpected number of operands for X86Local::RawFrmImm8");
826 HANDLE_OPERAND(immediate)
827 HANDLE_OPERAND(immediate)
829 case X86Local::RawFrmImm16:
830 // operand 1 is a 16-bit immediate
831 // operand 2 is a 16-bit immediate
832 HANDLE_OPERAND(immediate)
833 HANDLE_OPERAND(immediate)
835 case X86Local::MRM_F8:
836 if (Opcode == 0xc6) {
837 assert(numPhysicalOperands == 1 &&
838 "Unexpected number of operands for X86Local::MRM_F8");
839 HANDLE_OPERAND(immediate)
840 } else if (Opcode == 0xc7) {
841 assert(numPhysicalOperands == 1 &&
842 "Unexpected number of operands for X86Local::MRM_F8");
843 HANDLE_OPERAND(relocation)
846 case X86Local::MRM_C1:
847 case X86Local::MRM_C2:
848 case X86Local::MRM_C3:
849 case X86Local::MRM_C4:
850 case X86Local::MRM_C8:
851 case X86Local::MRM_C9:
852 case X86Local::MRM_CA:
853 case X86Local::MRM_CB:
854 case X86Local::MRM_E8:
855 case X86Local::MRM_F0:
856 case X86Local::MRM_F9:
857 case X86Local::MRM_D0:
858 case X86Local::MRM_D1:
859 case X86Local::MRM_D4:
860 case X86Local::MRM_D5:
861 case X86Local::MRM_D6:
862 case X86Local::MRM_D8:
863 case X86Local::MRM_D9:
864 case X86Local::MRM_DA:
865 case X86Local::MRM_DB:
866 case X86Local::MRM_DC:
867 case X86Local::MRM_DD:
868 case X86Local::MRM_DE:
869 case X86Local::MRM_DF:
874 #undef HANDLE_OPERAND
875 #undef HANDLE_OPTIONAL
878 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
879 // Special cases where the LLVM tables are not complete
881 #define MAP(from, to) \
882 case X86Local::MRM_##from: \
883 filter = new ExactFilter(0x##from); \
886 OpcodeType opcodeType = (OpcodeType)-1;
888 ModRMFilter* filter = NULL;
889 uint8_t opcodeToSet = 0;
892 default: llvm_unreachable("Invalid prefix!");
893 // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
898 opcodeType = TWOBYTE;
902 if (needsModRMForDecode(Form))
903 filter = new ModFilter(isRegFormat(Form));
905 filter = new DumbFilter();
907 #define EXTENSION_TABLE(n) case 0x##n:
908 TWO_BYTE_EXTENSION_TABLES
909 #undef EXTENSION_TABLE
912 llvm_unreachable("Unhandled two-byte extended opcode");
913 case X86Local::MRM0r:
914 case X86Local::MRM1r:
915 case X86Local::MRM2r:
916 case X86Local::MRM3r:
917 case X86Local::MRM4r:
918 case X86Local::MRM5r:
919 case X86Local::MRM6r:
920 case X86Local::MRM7r:
921 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
923 case X86Local::MRM0m:
924 case X86Local::MRM1m:
925 case X86Local::MRM2m:
926 case X86Local::MRM3m:
927 case X86Local::MRM4m:
928 case X86Local::MRM5m:
929 case X86Local::MRM6m:
930 case X86Local::MRM7m:
931 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
937 opcodeToSet = Opcode;
943 opcodeType = THREEBYTE_38;
946 if (needsModRMForDecode(Form))
947 filter = new ModFilter(isRegFormat(Form));
949 filter = new DumbFilter();
951 #define EXTENSION_TABLE(n) case 0x##n:
952 THREE_BYTE_38_EXTENSION_TABLES
953 #undef EXTENSION_TABLE
956 llvm_unreachable("Unhandled two-byte extended opcode");
957 case X86Local::MRM0r:
958 case X86Local::MRM1r:
959 case X86Local::MRM2r:
960 case X86Local::MRM3r:
961 case X86Local::MRM4r:
962 case X86Local::MRM5r:
963 case X86Local::MRM6r:
964 case X86Local::MRM7r:
965 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
967 case X86Local::MRM0m:
968 case X86Local::MRM1m:
969 case X86Local::MRM2m:
970 case X86Local::MRM3m:
971 case X86Local::MRM4m:
972 case X86Local::MRM5m:
973 case X86Local::MRM6m:
974 case X86Local::MRM7m:
975 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
981 opcodeToSet = Opcode;
986 opcodeType = THREEBYTE_3A;
987 if (needsModRMForDecode(Form))
988 filter = new ModFilter(isRegFormat(Form));
990 filter = new DumbFilter();
991 opcodeToSet = Opcode;
994 opcodeType = THREEBYTE_A6;
995 if (needsModRMForDecode(Form))
996 filter = new ModFilter(isRegFormat(Form));
998 filter = new DumbFilter();
999 opcodeToSet = Opcode;
1002 opcodeType = THREEBYTE_A7;
1003 if (needsModRMForDecode(Form))
1004 filter = new ModFilter(isRegFormat(Form));
1006 filter = new DumbFilter();
1007 opcodeToSet = Opcode;
1009 case X86Local::XOP8:
1010 opcodeType = XOP8_MAP;
1011 if (needsModRMForDecode(Form))
1012 filter = new ModFilter(isRegFormat(Form));
1014 filter = new DumbFilter();
1015 opcodeToSet = Opcode;
1017 case X86Local::XOP9:
1018 opcodeType = XOP9_MAP;
1021 if (needsModRMForDecode(Form))
1022 filter = new ModFilter(isRegFormat(Form));
1024 filter = new DumbFilter();
1026 #define EXTENSION_TABLE(n) case 0x##n:
1027 XOP9_MAP_EXTENSION_TABLES
1028 #undef EXTENSION_TABLE
1031 llvm_unreachable("Unhandled XOP9 extended opcode");
1032 case X86Local::MRM0r:
1033 case X86Local::MRM1r:
1034 case X86Local::MRM2r:
1035 case X86Local::MRM3r:
1036 case X86Local::MRM4r:
1037 case X86Local::MRM5r:
1038 case X86Local::MRM6r:
1039 case X86Local::MRM7r:
1040 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1042 case X86Local::MRM0m:
1043 case X86Local::MRM1m:
1044 case X86Local::MRM2m:
1045 case X86Local::MRM3m:
1046 case X86Local::MRM4m:
1047 case X86Local::MRM5m:
1048 case X86Local::MRM6m:
1049 case X86Local::MRM7m:
1050 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1055 } // switch (Opcode)
1056 opcodeToSet = Opcode;
1058 case X86Local::XOPA:
1059 opcodeType = XOPA_MAP;
1060 if (needsModRMForDecode(Form))
1061 filter = new ModFilter(isRegFormat(Form));
1063 filter = new DumbFilter();
1064 opcodeToSet = Opcode;
1074 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1075 assert(Form == X86Local::RawFrm);
1076 opcodeType = ONEBYTE;
1077 filter = new ExactFilter(Opcode);
1078 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1082 opcodeType = ONEBYTE;
1084 #define EXTENSION_TABLE(n) case 0x##n:
1085 ONE_BYTE_EXTENSION_TABLES
1086 #undef EXTENSION_TABLE
1089 llvm_unreachable("Fell through the cracks of a single-byte "
1091 case X86Local::MRM0r:
1092 case X86Local::MRM1r:
1093 case X86Local::MRM2r:
1094 case X86Local::MRM3r:
1095 case X86Local::MRM4r:
1096 case X86Local::MRM5r:
1097 case X86Local::MRM6r:
1098 case X86Local::MRM7r:
1099 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1101 case X86Local::MRM0m:
1102 case X86Local::MRM1m:
1103 case X86Local::MRM2m:
1104 case X86Local::MRM3m:
1105 case X86Local::MRM4m:
1106 case X86Local::MRM5m:
1107 case X86Local::MRM6m:
1108 case X86Local::MRM7m:
1109 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1124 llvm_unreachable("Unhandled escape opcode form");
1125 case X86Local::MRM0r:
1126 case X86Local::MRM1r:
1127 case X86Local::MRM2r:
1128 case X86Local::MRM3r:
1129 case X86Local::MRM4r:
1130 case X86Local::MRM5r:
1131 case X86Local::MRM6r:
1132 case X86Local::MRM7r:
1133 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1135 case X86Local::MRM0m:
1136 case X86Local::MRM1m:
1137 case X86Local::MRM2m:
1138 case X86Local::MRM3m:
1139 case X86Local::MRM4m:
1140 case X86Local::MRM5m:
1141 case X86Local::MRM6m:
1142 case X86Local::MRM7m:
1143 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1148 if (needsModRMForDecode(Form))
1149 filter = new ModFilter(isRegFormat(Form));
1151 filter = new DumbFilter();
1153 } // switch (Opcode)
1154 opcodeToSet = Opcode;
1155 } // switch (Prefix)
1157 assert(opcodeType != (OpcodeType)-1 &&
1158 "Opcode type not set");
1159 assert(filter && "Filter not set");
1161 if (Form == X86Local::AddRegFrm) {
1162 assert(((opcodeToSet & 7) == 0) &&
1163 "ADDREG_FRM opcode not aligned");
1165 uint8_t currentOpcode;
1167 for (currentOpcode = opcodeToSet;
1168 currentOpcode < opcodeToSet + 8;
1170 tables.setTableFields(opcodeType,
1174 UID, Is32Bit, IgnoresVEX_L);
1176 tables.setTableFields(opcodeType,
1180 UID, Is32Bit, IgnoresVEX_L);
1188 #define TYPE(str, type) if (s == str) return type;
1189 OperandType RecognizableInstr::typeFromString(const std::string &s,
1190 bool hasREX_WPrefix,
1191 bool hasOpSizePrefix,
1192 bool hasOpSize16Prefix) {
1193 if(hasREX_WPrefix) {
1194 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1196 TYPE("GR32", TYPE_R32)
1198 if(hasOpSizePrefix) {
1199 // For instructions with an OpSize prefix, a declared 16-bit register or
1200 // immediate encoding is special.
1201 TYPE("GR16", TYPE_Rv)
1202 TYPE("i16imm", TYPE_IMMv)
1204 if(hasOpSize16Prefix) {
1205 // For instructions with an OpSize16 prefix, a declared 32-bit register or
1206 // immediate encoding is special.
1207 TYPE("GR32", TYPE_Rv)
1209 TYPE("i16mem", TYPE_Mv)
1210 TYPE("i16imm", TYPE_IMM16)
1211 TYPE("i16i8imm", TYPE_IMMv)
1212 TYPE("GR16", TYPE_R16)
1213 TYPE("i32mem", TYPE_Mv)
1214 TYPE("i32imm", TYPE_IMMv)
1215 TYPE("i32i8imm", TYPE_IMM32)
1216 TYPE("u32u8imm", TYPE_IMM32)
1217 TYPE("GR32", TYPE_R32)
1218 TYPE("GR32orGR64", TYPE_R32)
1219 TYPE("i64mem", TYPE_Mv)
1220 TYPE("i64i32imm", TYPE_IMM64)
1221 TYPE("i64i8imm", TYPE_IMM64)
1222 TYPE("GR64", TYPE_R64)
1223 TYPE("i8mem", TYPE_M8)
1224 TYPE("i8imm", TYPE_IMM8)
1225 TYPE("GR8", TYPE_R8)
1226 TYPE("VR128", TYPE_XMM128)
1227 TYPE("VR128X", TYPE_XMM128)
1228 TYPE("f128mem", TYPE_M128)
1229 TYPE("f256mem", TYPE_M256)
1230 TYPE("f512mem", TYPE_M512)
1231 TYPE("FR64", TYPE_XMM64)
1232 TYPE("FR64X", TYPE_XMM64)
1233 TYPE("f64mem", TYPE_M64FP)
1234 TYPE("sdmem", TYPE_M64FP)
1235 TYPE("FR32", TYPE_XMM32)
1236 TYPE("FR32X", TYPE_XMM32)
1237 TYPE("f32mem", TYPE_M32FP)
1238 TYPE("ssmem", TYPE_M32FP)
1239 TYPE("RST", TYPE_ST)
1240 TYPE("i128mem", TYPE_M128)
1241 TYPE("i256mem", TYPE_M256)
1242 TYPE("i512mem", TYPE_M512)
1243 TYPE("i64i32imm_pcrel", TYPE_REL64)
1244 TYPE("i16imm_pcrel", TYPE_REL16)
1245 TYPE("i32imm_pcrel", TYPE_REL32)
1246 TYPE("SSECC", TYPE_IMM3)
1247 TYPE("AVXCC", TYPE_IMM5)
1248 TYPE("AVX512RC", TYPE_IMM32)
1249 TYPE("brtarget", TYPE_RELv)
1250 TYPE("uncondbrtarget", TYPE_RELv)
1251 TYPE("brtarget8", TYPE_REL8)
1252 TYPE("f80mem", TYPE_M80FP)
1253 TYPE("lea32mem", TYPE_LEA)
1254 TYPE("lea64_32mem", TYPE_LEA)
1255 TYPE("lea64mem", TYPE_LEA)
1256 TYPE("VR64", TYPE_MM64)
1257 TYPE("i64imm", TYPE_IMMv)
1258 TYPE("opaque32mem", TYPE_M1616)
1259 TYPE("opaque48mem", TYPE_M1632)
1260 TYPE("opaque80mem", TYPE_M1664)
1261 TYPE("opaque512mem", TYPE_M512)
1262 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1263 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1264 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1265 TYPE("offset8", TYPE_MOFFS8)
1266 TYPE("offset16", TYPE_MOFFS16)
1267 TYPE("offset32", TYPE_MOFFS32)
1268 TYPE("offset64", TYPE_MOFFS64)
1269 TYPE("VR256", TYPE_XMM256)
1270 TYPE("VR256X", TYPE_XMM256)
1271 TYPE("VR512", TYPE_XMM512)
1272 TYPE("VK1", TYPE_VK1)
1273 TYPE("VK1WM", TYPE_VK1)
1274 TYPE("VK8", TYPE_VK8)
1275 TYPE("VK8WM", TYPE_VK8)
1276 TYPE("VK16", TYPE_VK16)
1277 TYPE("VK16WM", TYPE_VK16)
1278 TYPE("GR16_NOAX", TYPE_Rv)
1279 TYPE("GR32_NOAX", TYPE_Rv)
1280 TYPE("GR64_NOAX", TYPE_R64)
1281 TYPE("vx32mem", TYPE_M32)
1282 TYPE("vy32mem", TYPE_M32)
1283 TYPE("vz32mem", TYPE_M32)
1284 TYPE("vx64mem", TYPE_M64)
1285 TYPE("vy64mem", TYPE_M64)
1286 TYPE("vy64xmem", TYPE_M64)
1287 TYPE("vz64mem", TYPE_M64)
1288 errs() << "Unhandled type string " << s << "\n";
1289 llvm_unreachable("Unhandled type string");
1293 #define ENCODING(str, encoding) if (s == str) return encoding;
1294 OperandEncoding RecognizableInstr::immediateEncodingFromString
1295 (const std::string &s,
1296 bool hasOpSizePrefix) {
1297 if(!hasOpSizePrefix) {
1298 // For instructions without an OpSize prefix, a declared 16-bit register or
1299 // immediate encoding is special.
1300 ENCODING("i16imm", ENCODING_IW)
1302 ENCODING("i32i8imm", ENCODING_IB)
1303 ENCODING("u32u8imm", ENCODING_IB)
1304 ENCODING("SSECC", ENCODING_IB)
1305 ENCODING("AVXCC", ENCODING_IB)
1306 ENCODING("AVX512RC", ENCODING_IB)
1307 ENCODING("i16imm", ENCODING_Iv)
1308 ENCODING("i16i8imm", ENCODING_IB)
1309 ENCODING("i32imm", ENCODING_Iv)
1310 ENCODING("i64i32imm", ENCODING_ID)
1311 ENCODING("i64i8imm", ENCODING_IB)
1312 ENCODING("i8imm", ENCODING_IB)
1313 // This is not a typo. Instructions like BLENDVPD put
1314 // register IDs in 8-bit immediates nowadays.
1315 ENCODING("FR32", ENCODING_IB)
1316 ENCODING("FR64", ENCODING_IB)
1317 ENCODING("VR128", ENCODING_IB)
1318 ENCODING("VR256", ENCODING_IB)
1319 ENCODING("FR32X", ENCODING_IB)
1320 ENCODING("FR64X", ENCODING_IB)
1321 ENCODING("VR128X", ENCODING_IB)
1322 ENCODING("VR256X", ENCODING_IB)
1323 ENCODING("VR512", ENCODING_IB)
1324 errs() << "Unhandled immediate encoding " << s << "\n";
1325 llvm_unreachable("Unhandled immediate encoding");
1328 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1329 (const std::string &s,
1330 bool hasOpSizePrefix) {
1331 ENCODING("RST", ENCODING_FP)
1332 ENCODING("GR16", ENCODING_RM)
1333 ENCODING("GR32", ENCODING_RM)
1334 ENCODING("GR32orGR64", ENCODING_RM)
1335 ENCODING("GR64", ENCODING_RM)
1336 ENCODING("GR8", ENCODING_RM)
1337 ENCODING("VR128", ENCODING_RM)
1338 ENCODING("VR128X", ENCODING_RM)
1339 ENCODING("FR64", ENCODING_RM)
1340 ENCODING("FR32", ENCODING_RM)
1341 ENCODING("FR64X", ENCODING_RM)
1342 ENCODING("FR32X", ENCODING_RM)
1343 ENCODING("VR64", ENCODING_RM)
1344 ENCODING("VR256", ENCODING_RM)
1345 ENCODING("VR256X", ENCODING_RM)
1346 ENCODING("VR512", ENCODING_RM)
1347 ENCODING("VK1", ENCODING_RM)
1348 ENCODING("VK8", ENCODING_RM)
1349 ENCODING("VK16", ENCODING_RM)
1350 errs() << "Unhandled R/M register encoding " << s << "\n";
1351 llvm_unreachable("Unhandled R/M register encoding");
1354 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1355 (const std::string &s,
1356 bool hasOpSizePrefix) {
1357 ENCODING("GR16", ENCODING_REG)
1358 ENCODING("GR32", ENCODING_REG)
1359 ENCODING("GR32orGR64", ENCODING_REG)
1360 ENCODING("GR64", ENCODING_REG)
1361 ENCODING("GR8", ENCODING_REG)
1362 ENCODING("VR128", ENCODING_REG)
1363 ENCODING("FR64", ENCODING_REG)
1364 ENCODING("FR32", ENCODING_REG)
1365 ENCODING("VR64", ENCODING_REG)
1366 ENCODING("SEGMENT_REG", ENCODING_REG)
1367 ENCODING("DEBUG_REG", ENCODING_REG)
1368 ENCODING("CONTROL_REG", ENCODING_REG)
1369 ENCODING("VR256", ENCODING_REG)
1370 ENCODING("VR256X", ENCODING_REG)
1371 ENCODING("VR128X", ENCODING_REG)
1372 ENCODING("FR64X", ENCODING_REG)
1373 ENCODING("FR32X", ENCODING_REG)
1374 ENCODING("VR512", ENCODING_REG)
1375 ENCODING("VK1", ENCODING_REG)
1376 ENCODING("VK8", ENCODING_REG)
1377 ENCODING("VK16", ENCODING_REG)
1378 ENCODING("VK1WM", ENCODING_REG)
1379 ENCODING("VK8WM", ENCODING_REG)
1380 ENCODING("VK16WM", ENCODING_REG)
1381 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1382 llvm_unreachable("Unhandled reg/opcode register encoding");
1385 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1386 (const std::string &s,
1387 bool hasOpSizePrefix) {
1388 ENCODING("GR32", ENCODING_VVVV)
1389 ENCODING("GR64", ENCODING_VVVV)
1390 ENCODING("FR32", ENCODING_VVVV)
1391 ENCODING("FR64", ENCODING_VVVV)
1392 ENCODING("VR128", ENCODING_VVVV)
1393 ENCODING("VR256", ENCODING_VVVV)
1394 ENCODING("FR32X", ENCODING_VVVV)
1395 ENCODING("FR64X", ENCODING_VVVV)
1396 ENCODING("VR128X", ENCODING_VVVV)
1397 ENCODING("VR256X", ENCODING_VVVV)
1398 ENCODING("VR512", ENCODING_VVVV)
1399 ENCODING("VK1", ENCODING_VVVV)
1400 ENCODING("VK8", ENCODING_VVVV)
1401 ENCODING("VK16", ENCODING_VVVV)
1402 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1403 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1406 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1407 (const std::string &s,
1408 bool hasOpSizePrefix) {
1409 ENCODING("VK1WM", ENCODING_WRITEMASK)
1410 ENCODING("VK8WM", ENCODING_WRITEMASK)
1411 ENCODING("VK16WM", ENCODING_WRITEMASK)
1412 errs() << "Unhandled mask register encoding " << s << "\n";
1413 llvm_unreachable("Unhandled mask register encoding");
1416 OperandEncoding RecognizableInstr::memoryEncodingFromString
1417 (const std::string &s,
1418 bool hasOpSizePrefix) {
1419 ENCODING("i16mem", ENCODING_RM)
1420 ENCODING("i32mem", ENCODING_RM)
1421 ENCODING("i64mem", ENCODING_RM)
1422 ENCODING("i8mem", ENCODING_RM)
1423 ENCODING("ssmem", ENCODING_RM)
1424 ENCODING("sdmem", ENCODING_RM)
1425 ENCODING("f128mem", ENCODING_RM)
1426 ENCODING("f256mem", ENCODING_RM)
1427 ENCODING("f512mem", ENCODING_RM)
1428 ENCODING("f64mem", ENCODING_RM)
1429 ENCODING("f32mem", ENCODING_RM)
1430 ENCODING("i128mem", ENCODING_RM)
1431 ENCODING("i256mem", ENCODING_RM)
1432 ENCODING("i512mem", ENCODING_RM)
1433 ENCODING("f80mem", ENCODING_RM)
1434 ENCODING("lea32mem", ENCODING_RM)
1435 ENCODING("lea64_32mem", ENCODING_RM)
1436 ENCODING("lea64mem", ENCODING_RM)
1437 ENCODING("opaque32mem", ENCODING_RM)
1438 ENCODING("opaque48mem", ENCODING_RM)
1439 ENCODING("opaque80mem", ENCODING_RM)
1440 ENCODING("opaque512mem", ENCODING_RM)
1441 ENCODING("vx32mem", ENCODING_RM)
1442 ENCODING("vy32mem", ENCODING_RM)
1443 ENCODING("vz32mem", ENCODING_RM)
1444 ENCODING("vx64mem", ENCODING_RM)
1445 ENCODING("vy64mem", ENCODING_RM)
1446 ENCODING("vy64xmem", ENCODING_RM)
1447 ENCODING("vz64mem", ENCODING_RM)
1448 errs() << "Unhandled memory encoding " << s << "\n";
1449 llvm_unreachable("Unhandled memory encoding");
1452 OperandEncoding RecognizableInstr::relocationEncodingFromString
1453 (const std::string &s,
1454 bool hasOpSizePrefix) {
1455 if(!hasOpSizePrefix) {
1456 // For instructions without an OpSize prefix, a declared 16-bit register or
1457 // immediate encoding is special.
1458 ENCODING("i16imm", ENCODING_IW)
1460 ENCODING("i16imm", ENCODING_Iv)
1461 ENCODING("i16i8imm", ENCODING_IB)
1462 ENCODING("i32imm", ENCODING_Iv)
1463 ENCODING("i32i8imm", ENCODING_IB)
1464 ENCODING("i64i32imm", ENCODING_ID)
1465 ENCODING("i64i8imm", ENCODING_IB)
1466 ENCODING("i8imm", ENCODING_IB)
1467 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1468 ENCODING("i16imm_pcrel", ENCODING_IW)
1469 ENCODING("i32imm_pcrel", ENCODING_ID)
1470 ENCODING("brtarget", ENCODING_Iv)
1471 ENCODING("brtarget8", ENCODING_IB)
1472 ENCODING("i64imm", ENCODING_IO)
1473 ENCODING("offset8", ENCODING_Ia)
1474 ENCODING("offset16", ENCODING_Ia)
1475 ENCODING("offset32", ENCODING_Ia)
1476 ENCODING("offset64", ENCODING_Ia)
1477 errs() << "Unhandled relocation encoding " << s << "\n";
1478 llvm_unreachable("Unhandled relocation encoding");
1481 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1482 (const std::string &s,
1483 bool hasOpSizePrefix) {
1484 ENCODING("GR32", ENCODING_Rv)
1485 ENCODING("GR64", ENCODING_RO)
1486 ENCODING("GR16", ENCODING_Rv)
1487 ENCODING("GR8", ENCODING_RB)
1488 ENCODING("GR16_NOAX", ENCODING_Rv)
1489 ENCODING("GR32_NOAX", ENCODING_Rv)
1490 ENCODING("GR64_NOAX", ENCODING_RO)
1491 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1492 llvm_unreachable("Unhandled opcode modifier encoding");