1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
39 // A clone of X86 since we can't depend on something that is generated.
49 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
50 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
51 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
52 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
54 #define MAP(from, to) MRM_##from = to,
65 D8 = 3, D9 = 4, DA = 5, DB = 6,
66 DC = 7, DD = 8, DE = 9, DF = 10,
69 P_0F_AE = 16, P_0F_01 = 17
73 // If rows are added to the opcode extension tables, then corresponding entries
74 // must be added here.
76 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
77 // that byte to ONE_BYTE_EXTENSION_TABLES.
79 // If the row corresponds to two bytes where the first is 0f, add an entry for
80 // the second byte to TWO_BYTE_EXTENSION_TABLES.
82 // If the row corresponds to some other set of bytes, you will need to modify
83 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
84 // to the X86 TD files, except in two cases: if the first two bytes of such a
85 // new combination are 0f 38 or 0f 3a, you just have to add maps called
86 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
87 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
88 // in RecognizableInstr::emitDecodePath().
90 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(d0) \
101 EXTENSION_TABLE(d1) \
102 EXTENSION_TABLE(d2) \
103 EXTENSION_TABLE(d3) \
104 EXTENSION_TABLE(f6) \
105 EXTENSION_TABLE(f7) \
106 EXTENSION_TABLE(fe) \
109 #define TWO_BYTE_EXTENSION_TABLES \
110 EXTENSION_TABLE(00) \
111 EXTENSION_TABLE(01) \
112 EXTENSION_TABLE(18) \
113 EXTENSION_TABLE(71) \
114 EXTENSION_TABLE(72) \
115 EXTENSION_TABLE(73) \
116 EXTENSION_TABLE(ae) \
117 EXTENSION_TABLE(b9) \
118 EXTENSION_TABLE(ba) \
121 using namespace X86Disassembler;
123 /// needsModRMForDecode - Indicates whether a particular instruction requires a
124 /// ModR/M byte for the instruction to be properly decoded. For example, a
125 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
128 /// @param form - The form of the instruction.
129 /// @return - true if the form implies that a ModR/M byte is required, false
131 static bool needsModRMForDecode(uint8_t form) {
132 if (form == X86Local::MRMDestReg ||
133 form == X86Local::MRMDestMem ||
134 form == X86Local::MRMSrcReg ||
135 form == X86Local::MRMSrcMem ||
136 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
137 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
143 /// isRegFormat - Indicates whether a particular form requires the Mod field of
144 /// the ModR/M byte to be 0b11.
146 /// @param form - The form of the instruction.
147 /// @return - true if the form implies that Mod must be 0b11, false
149 static bool isRegFormat(uint8_t form) {
150 if (form == X86Local::MRMDestReg ||
151 form == X86Local::MRMSrcReg ||
152 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
158 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
159 /// Useful for switch statements and the like.
161 /// @param init - A reference to the BitsInit to be decoded.
162 /// @return - The field, with the first bit in the BitsInit as the lowest
164 static uint8_t byteFromBitsInit(BitsInit &init) {
165 int width = init.getNumBits();
167 assert(width <= 8 && "Field is too large for uint8_t!");
174 for (index = 0; index < width; index++) {
175 if (static_cast<BitInit*>(init.getBit(index))->getValue())
184 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
185 /// name of the field.
187 /// @param rec - The record from which to extract the value.
188 /// @param name - The name of the field in the record.
189 /// @return - The field, as translated by byteFromBitsInit().
190 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
191 BitsInit* bits = rec->getValueAsBitsInit(name);
192 return byteFromBitsInit(*bits);
195 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
196 const CodeGenInstruction &insn,
201 Name = Rec->getName();
202 Spec = &tables.specForUID(UID);
204 if (!Rec->isSubClassOf("X86Inst")) {
205 ShouldBeEmitted = false;
209 Prefix = byteFromRec(Rec, "Prefix");
210 Opcode = byteFromRec(Rec, "Opcode");
211 Form = byteFromRec(Rec, "FormBits");
212 SegOvr = byteFromRec(Rec, "SegOvrBits");
214 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
215 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
216 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
217 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
218 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
220 Name = Rec->getName();
221 AsmString = Rec->getValueAsString("AsmString");
223 Operands = &insn.OperandList;
225 IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos);
226 HasFROperands = false;
228 ShouldBeEmitted = true;
231 void RecognizableInstr::processInstr(DisassemblerTables &tables,
232 const CodeGenInstruction &insn,
235 // Ignore "asm parser only" instructions.
236 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
239 RecognizableInstr recogInstr(tables, insn, uid);
241 recogInstr.emitInstructionSpecifier(tables);
243 if (recogInstr.shouldBeEmitted())
244 recogInstr.emitDecodePath(tables);
247 InstructionContext RecognizableInstr::insnContext() const {
248 InstructionContext insnContext;
250 if (Name.find("64") != Name.npos || HasREX_WPrefix) {
251 if (HasREX_WPrefix && HasOpSizePrefix)
252 insnContext = IC_64BIT_REXW_OPSIZE;
253 else if (HasOpSizePrefix)
254 insnContext = IC_64BIT_OPSIZE;
255 else if (HasREX_WPrefix && Prefix == X86Local::XS)
256 insnContext = IC_64BIT_REXW_XS;
257 else if (HasREX_WPrefix && Prefix == X86Local::XD)
258 insnContext = IC_64BIT_REXW_XD;
259 else if (Prefix == X86Local::XD)
260 insnContext = IC_64BIT_XD;
261 else if (Prefix == X86Local::XS)
262 insnContext = IC_64BIT_XS;
263 else if (HasREX_WPrefix)
264 insnContext = IC_64BIT_REXW;
266 insnContext = IC_64BIT;
269 insnContext = IC_OPSIZE;
270 else if (Prefix == X86Local::XD)
272 else if (Prefix == X86Local::XS)
281 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
282 // Filter out intrinsics
284 if (!Rec->isSubClassOf("X86Inst"))
285 return FILTER_STRONG;
287 if (Form == X86Local::Pseudo ||
289 return FILTER_STRONG;
291 if (Form == X86Local::MRMInitReg)
292 return FILTER_STRONG;
295 // Filter out instructions with a LOCK prefix;
296 // prefer forms that do not have the prefix
300 // Filter out artificial instructions
302 if (Name.find("TAILJMP") != Name.npos ||
303 Name.find("_Int") != Name.npos ||
304 Name.find("_int") != Name.npos ||
305 Name.find("Int_") != Name.npos ||
306 Name.find("_NOREX") != Name.npos ||
307 Name.find("_TC") != Name.npos ||
308 Name.find("EH_RETURN") != Name.npos ||
309 Name.find("V_SET") != Name.npos ||
310 Name.find("LOCK_") != Name.npos ||
311 Name.find("WIN") != Name.npos)
312 return FILTER_STRONG;
316 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
318 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
321 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
323 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
325 if (Name.find("Fs") != Name.npos)
327 if (Name == "MOVLPDrr" ||
328 Name == "MOVLPSrr" ||
334 Name == "MOVSX16rm8" ||
335 Name == "MOVSX16rr8" ||
336 Name == "MOVZX16rm8" ||
337 Name == "MOVZX16rr8" ||
338 Name == "PUSH32i16" ||
339 Name == "PUSH64i16" ||
340 Name == "MOVPQI2QImr" ||
345 Name == "MMX_MOVD64rrv164" ||
346 Name == "CRC32m16" ||
347 Name == "MOV64ri64i32" ||
351 // Filter out instructions with segment override prefixes.
352 // They're too messy to handle now and we'll special case them if needed.
355 return FILTER_STRONG;
357 // Filter out instructions that can't be printed.
359 if (AsmString.size() == 0)
360 return FILTER_STRONG;
362 // Filter out instructions with subreg operands.
364 if (AsmString.find("subreg") != AsmString.npos)
365 return FILTER_STRONG;
367 if (HasFROperands && Name.find("MOV") != Name.npos &&
368 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
369 (Name.find("to") != Name.npos)))
372 return FILTER_NORMAL;
375 void RecognizableInstr::handleOperand(
377 unsigned &operandIndex,
378 unsigned &physicalOperandIndex,
379 unsigned &numPhysicalOperands,
380 unsigned *operandMapping,
381 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
383 if (physicalOperandIndex >= numPhysicalOperands)
386 assert(physicalOperandIndex < numPhysicalOperands);
389 while (operandMapping[operandIndex] != operandIndex) {
390 Spec->operands[operandIndex].encoding = ENCODING_DUP;
391 Spec->operands[operandIndex].type =
392 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
396 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
398 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
400 Spec->operands[operandIndex].type = typeFromString(typeName,
406 ++physicalOperandIndex;
409 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
412 if (!Rec->isSubClassOf("X86Inst"))
417 Spec->filtered = true;
420 ShouldBeEmitted = false;
426 Spec->insnContext = insnContext();
428 const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
430 unsigned operandIndex;
431 unsigned numOperands = OperandList.size();
432 unsigned numPhysicalOperands = 0;
434 // operandMapping maps from operands in OperandList to their originals.
435 // If operandMapping[i] != i, then the entry is a duplicate.
436 unsigned operandMapping[X86_MAX_OPERANDS];
438 bool hasFROperands = false;
440 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
442 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
443 if (OperandList[operandIndex].Constraints.size()) {
444 const CodeGenInstruction::ConstraintInfo &Constraint =
445 OperandList[operandIndex].Constraints[0];
446 if (Constraint.isTied()) {
447 operandMapping[operandIndex] = Constraint.getTiedOperand();
449 ++numPhysicalOperands;
450 operandMapping[operandIndex] = operandIndex;
453 ++numPhysicalOperands;
454 operandMapping[operandIndex] = operandIndex;
457 const std::string &recName = OperandList[operandIndex].Rec->getName();
459 if (recName.find("FR") != recName.npos)
460 hasFROperands = true;
463 if (hasFROperands && Name.find("MOV") != Name.npos &&
464 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
465 (Name.find("to") != Name.npos)))
466 ShouldBeEmitted = false;
468 if (!ShouldBeEmitted)
471 #define HANDLE_OPERAND(class) \
472 handleOperand(false, \
474 physicalOperandIndex, \
475 numPhysicalOperands, \
477 class##EncodingFromString);
479 #define HANDLE_OPTIONAL(class) \
480 handleOperand(true, \
482 physicalOperandIndex, \
483 numPhysicalOperands, \
485 class##EncodingFromString);
487 // operandIndex should always be < numOperands
489 // physicalOperandIndex should always be < numPhysicalOperands
490 unsigned physicalOperandIndex = 0;
493 case X86Local::RawFrm:
494 // Operand 1 (optional) is an address or immediate.
495 // Operand 2 (optional) is an immediate.
496 assert(numPhysicalOperands <= 2 &&
497 "Unexpected number of operands for RawFrm");
498 HANDLE_OPTIONAL(relocation)
499 HANDLE_OPTIONAL(immediate)
501 case X86Local::AddRegFrm:
502 // Operand 1 is added to the opcode.
503 // Operand 2 (optional) is an address.
504 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
505 "Unexpected number of operands for AddRegFrm");
506 HANDLE_OPERAND(opcodeModifier)
507 HANDLE_OPTIONAL(relocation)
509 case X86Local::MRMDestReg:
510 // Operand 1 is a register operand in the R/M field.
511 // Operand 2 is a register operand in the Reg/Opcode field.
512 // Operand 3 (optional) is an immediate.
513 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
514 "Unexpected number of operands for MRMDestRegFrm");
515 HANDLE_OPERAND(rmRegister)
516 HANDLE_OPERAND(roRegister)
517 HANDLE_OPTIONAL(immediate)
519 case X86Local::MRMDestMem:
520 // Operand 1 is a memory operand (possibly SIB-extended)
521 // Operand 2 is a register operand in the Reg/Opcode field.
522 // Operand 3 (optional) is an immediate.
523 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
524 "Unexpected number of operands for MRMDestMemFrm");
525 HANDLE_OPERAND(memory)
526 HANDLE_OPERAND(roRegister)
527 HANDLE_OPTIONAL(immediate)
529 case X86Local::MRMSrcReg:
530 // Operand 1 is a register operand in the Reg/Opcode field.
531 // Operand 2 is a register operand in the R/M field.
532 // Operand 3 (optional) is an immediate.
533 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
534 "Unexpected number of operands for MRMSrcRegFrm");
535 HANDLE_OPERAND(roRegister)
536 HANDLE_OPERAND(rmRegister)
539 // FIXME: In AVX, the register below becomes the one encoded
540 // in ModRMVEX and the one above the one in the VEX.VVVV field
541 HANDLE_OPTIONAL(rmRegister)
543 HANDLE_OPTIONAL(immediate)
545 case X86Local::MRMSrcMem:
546 // Operand 1 is a register operand in the Reg/Opcode field.
547 // Operand 2 is a memory operand (possibly SIB-extended)
548 // Operand 3 (optional) is an immediate.
549 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
550 "Unexpected number of operands for MRMSrcMemFrm");
551 HANDLE_OPERAND(roRegister)
554 // FIXME: In AVX, the register below becomes the one encoded
555 // in ModRMVEX and the one above the one in the VEX.VVVV field
556 HANDLE_OPTIONAL(rmRegister)
558 HANDLE_OPERAND(memory)
559 HANDLE_OPTIONAL(immediate)
561 case X86Local::MRM0r:
562 case X86Local::MRM1r:
563 case X86Local::MRM2r:
564 case X86Local::MRM3r:
565 case X86Local::MRM4r:
566 case X86Local::MRM5r:
567 case X86Local::MRM6r:
568 case X86Local::MRM7r:
569 // Operand 1 is a register operand in the R/M field.
570 // Operand 2 (optional) is an immediate or relocation.
571 assert(numPhysicalOperands <= 2 &&
572 "Unexpected number of operands for MRMnRFrm");
573 HANDLE_OPTIONAL(rmRegister)
574 HANDLE_OPTIONAL(relocation)
576 case X86Local::MRM0m:
577 case X86Local::MRM1m:
578 case X86Local::MRM2m:
579 case X86Local::MRM3m:
580 case X86Local::MRM4m:
581 case X86Local::MRM5m:
582 case X86Local::MRM6m:
583 case X86Local::MRM7m:
584 // Operand 1 is a memory operand (possibly SIB-extended)
585 // Operand 2 (optional) is an immediate or relocation.
586 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
587 "Unexpected number of operands for MRMnMFrm");
588 HANDLE_OPERAND(memory)
589 HANDLE_OPTIONAL(relocation)
591 case X86Local::RawFrmImm8:
592 // operand 1 is a 16-bit immediate
593 // operand 2 is an 8-bit immediate
594 assert(numPhysicalOperands == 2 &&
595 "Unexpected number of operands for X86Local::RawFrmImm8");
596 HANDLE_OPERAND(immediate)
597 HANDLE_OPERAND(immediate)
599 case X86Local::RawFrmImm16:
600 // operand 1 is a 16-bit immediate
601 // operand 2 is a 16-bit immediate
602 HANDLE_OPERAND(immediate)
603 HANDLE_OPERAND(immediate)
605 case X86Local::MRMInitReg:
610 #undef HANDLE_OPERAND
611 #undef HANDLE_OPTIONAL
614 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
615 // Special cases where the LLVM tables are not complete
617 #define MAP(from, to) \
618 case X86Local::MRM_##from: \
619 filter = new ExactFilter(0x##from); \
622 OpcodeType opcodeType = (OpcodeType)-1;
624 ModRMFilter* filter = NULL;
625 uint8_t opcodeToSet = 0;
628 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
632 opcodeType = TWOBYTE;
636 if (needsModRMForDecode(Form))
637 filter = new ModFilter(isRegFormat(Form));
639 filter = new DumbFilter();
641 #define EXTENSION_TABLE(n) case 0x##n:
642 TWO_BYTE_EXTENSION_TABLES
643 #undef EXTENSION_TABLE
646 llvm_unreachable("Unhandled two-byte extended opcode");
647 case X86Local::MRM0r:
648 case X86Local::MRM1r:
649 case X86Local::MRM2r:
650 case X86Local::MRM3r:
651 case X86Local::MRM4r:
652 case X86Local::MRM5r:
653 case X86Local::MRM6r:
654 case X86Local::MRM7r:
655 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
657 case X86Local::MRM0m:
658 case X86Local::MRM1m:
659 case X86Local::MRM2m:
660 case X86Local::MRM3m:
661 case X86Local::MRM4m:
662 case X86Local::MRM5m:
663 case X86Local::MRM6m:
664 case X86Local::MRM7m:
665 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
671 opcodeToSet = Opcode;
674 opcodeType = THREEBYTE_38;
675 if (needsModRMForDecode(Form))
676 filter = new ModFilter(isRegFormat(Form));
678 filter = new DumbFilter();
679 opcodeToSet = Opcode;
682 opcodeType = THREEBYTE_3A;
683 if (needsModRMForDecode(Form))
684 filter = new ModFilter(isRegFormat(Form));
686 filter = new DumbFilter();
687 opcodeToSet = Opcode;
697 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
698 opcodeType = ONEBYTE;
699 if (Form == X86Local::AddRegFrm) {
700 Spec->modifierType = MODIFIER_MODRM;
701 Spec->modifierBase = Opcode;
702 filter = new AddRegEscapeFilter(Opcode);
704 filter = new EscapeFilter(true, Opcode);
706 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
709 opcodeType = ONEBYTE;
711 #define EXTENSION_TABLE(n) case 0x##n:
712 ONE_BYTE_EXTENSION_TABLES
713 #undef EXTENSION_TABLE
716 llvm_unreachable("Fell through the cracks of a single-byte "
718 case X86Local::MRM0r:
719 case X86Local::MRM1r:
720 case X86Local::MRM2r:
721 case X86Local::MRM3r:
722 case X86Local::MRM4r:
723 case X86Local::MRM5r:
724 case X86Local::MRM6r:
725 case X86Local::MRM7r:
726 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
728 case X86Local::MRM0m:
729 case X86Local::MRM1m:
730 case X86Local::MRM2m:
731 case X86Local::MRM3m:
732 case X86Local::MRM4m:
733 case X86Local::MRM5m:
734 case X86Local::MRM6m:
735 case X86Local::MRM7m:
736 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
749 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
752 if (needsModRMForDecode(Form))
753 filter = new ModFilter(isRegFormat(Form));
755 filter = new DumbFilter();
758 opcodeToSet = Opcode;
761 assert(opcodeType != (OpcodeType)-1 &&
762 "Opcode type not set");
763 assert(filter && "Filter not set");
765 if (Form == X86Local::AddRegFrm) {
766 if(Spec->modifierType != MODIFIER_MODRM) {
767 assert(opcodeToSet < 0xf9 &&
768 "Not enough room for all ADDREG_FRM operands");
770 uint8_t currentOpcode;
772 for (currentOpcode = opcodeToSet;
773 currentOpcode < opcodeToSet + 8;
775 tables.setTableFields(opcodeType,
781 Spec->modifierType = MODIFIER_OPCODE;
782 Spec->modifierBase = opcodeToSet;
784 // modifierBase was set where MODIFIER_MODRM was set
785 tables.setTableFields(opcodeType,
792 tables.setTableFields(opcodeType,
798 Spec->modifierType = MODIFIER_NONE;
799 Spec->modifierBase = opcodeToSet;
807 #define TYPE(str, type) if (s == str) return type;
808 OperandType RecognizableInstr::typeFromString(const std::string &s,
811 bool hasOpSizePrefix) {
813 // For SSE instructions, we ignore the OpSize prefix and force operand
815 TYPE("GR16", TYPE_R16)
816 TYPE("GR32", TYPE_R32)
817 TYPE("GR64", TYPE_R64)
820 // For instructions with a REX_W prefix, a declared 32-bit register encoding
822 TYPE("GR32", TYPE_R32)
824 if(!hasOpSizePrefix) {
825 // For instructions without an OpSize prefix, a declared 16-bit register or
826 // immediate encoding is special.
827 TYPE("GR16", TYPE_R16)
828 TYPE("i16imm", TYPE_IMM16)
830 TYPE("i16mem", TYPE_Mv)
831 TYPE("i16imm", TYPE_IMMv)
832 TYPE("i16i8imm", TYPE_IMMv)
833 TYPE("GR16", TYPE_Rv)
834 TYPE("i32mem", TYPE_Mv)
835 TYPE("i32imm", TYPE_IMMv)
836 TYPE("i32i8imm", TYPE_IMM32)
837 TYPE("GR32", TYPE_Rv)
838 TYPE("i64mem", TYPE_Mv)
839 TYPE("i64i32imm", TYPE_IMM64)
840 TYPE("i64i8imm", TYPE_IMM64)
841 TYPE("GR64", TYPE_R64)
842 TYPE("i8mem", TYPE_M8)
843 TYPE("i8imm", TYPE_IMM8)
845 TYPE("VR128", TYPE_XMM128)
846 TYPE("f128mem", TYPE_M128)
847 TYPE("f256mem", TYPE_M256)
848 TYPE("FR64", TYPE_XMM64)
849 TYPE("f64mem", TYPE_M64FP)
850 TYPE("sdmem", TYPE_M64FP)
851 TYPE("FR32", TYPE_XMM32)
852 TYPE("f32mem", TYPE_M32FP)
853 TYPE("ssmem", TYPE_M32FP)
855 TYPE("i128mem", TYPE_M128)
856 TYPE("i64i32imm_pcrel", TYPE_REL64)
857 TYPE("i16imm_pcrel", TYPE_REL16)
858 TYPE("i32imm_pcrel", TYPE_REL32)
859 TYPE("SSECC", TYPE_IMM3)
860 TYPE("brtarget", TYPE_RELv)
861 TYPE("brtarget8", TYPE_REL8)
862 TYPE("f80mem", TYPE_M80FP)
863 TYPE("lea32mem", TYPE_LEA)
864 TYPE("lea64_32mem", TYPE_LEA)
865 TYPE("lea64mem", TYPE_LEA)
866 TYPE("VR64", TYPE_MM64)
867 TYPE("i64imm", TYPE_IMMv)
868 TYPE("opaque32mem", TYPE_M1616)
869 TYPE("opaque48mem", TYPE_M1632)
870 TYPE("opaque80mem", TYPE_M1664)
871 TYPE("opaque512mem", TYPE_M512)
872 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
873 TYPE("DEBUG_REG", TYPE_DEBUGREG)
874 TYPE("CONTROL_REG", TYPE_CONTROLREG)
875 TYPE("offset8", TYPE_MOFFS8)
876 TYPE("offset16", TYPE_MOFFS16)
877 TYPE("offset32", TYPE_MOFFS32)
878 TYPE("offset64", TYPE_MOFFS64)
879 errs() << "Unhandled type string " << s << "\n";
880 llvm_unreachable("Unhandled type string");
884 #define ENCODING(str, encoding) if (s == str) return encoding;
885 OperandEncoding RecognizableInstr::immediateEncodingFromString
886 (const std::string &s,
887 bool hasOpSizePrefix) {
888 if(!hasOpSizePrefix) {
889 // For instructions without an OpSize prefix, a declared 16-bit register or
890 // immediate encoding is special.
891 ENCODING("i16imm", ENCODING_IW)
893 ENCODING("i32i8imm", ENCODING_IB)
894 ENCODING("SSECC", ENCODING_IB)
895 ENCODING("i16imm", ENCODING_Iv)
896 ENCODING("i16i8imm", ENCODING_IB)
897 ENCODING("i32imm", ENCODING_Iv)
898 ENCODING("i64i32imm", ENCODING_ID)
899 ENCODING("i64i8imm", ENCODING_IB)
900 ENCODING("i8imm", ENCODING_IB)
901 errs() << "Unhandled immediate encoding " << s << "\n";
902 llvm_unreachable("Unhandled immediate encoding");
905 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
906 (const std::string &s,
907 bool hasOpSizePrefix) {
908 ENCODING("GR16", ENCODING_RM)
909 ENCODING("GR32", ENCODING_RM)
910 ENCODING("GR64", ENCODING_RM)
911 ENCODING("GR8", ENCODING_RM)
912 ENCODING("VR128", ENCODING_RM)
913 ENCODING("FR64", ENCODING_RM)
914 ENCODING("FR32", ENCODING_RM)
915 ENCODING("VR64", ENCODING_RM)
916 errs() << "Unhandled R/M register encoding " << s << "\n";
917 llvm_unreachable("Unhandled R/M register encoding");
920 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
921 (const std::string &s,
922 bool hasOpSizePrefix) {
923 ENCODING("GR16", ENCODING_REG)
924 ENCODING("GR32", ENCODING_REG)
925 ENCODING("GR64", ENCODING_REG)
926 ENCODING("GR8", ENCODING_REG)
927 ENCODING("VR128", ENCODING_REG)
928 ENCODING("FR64", ENCODING_REG)
929 ENCODING("FR32", ENCODING_REG)
930 ENCODING("VR64", ENCODING_REG)
931 ENCODING("SEGMENT_REG", ENCODING_REG)
932 ENCODING("DEBUG_REG", ENCODING_REG)
933 ENCODING("CONTROL_REG", ENCODING_REG)
934 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
935 llvm_unreachable("Unhandled reg/opcode register encoding");
938 OperandEncoding RecognizableInstr::memoryEncodingFromString
939 (const std::string &s,
940 bool hasOpSizePrefix) {
941 ENCODING("i16mem", ENCODING_RM)
942 ENCODING("i32mem", ENCODING_RM)
943 ENCODING("i64mem", ENCODING_RM)
944 ENCODING("i8mem", ENCODING_RM)
945 ENCODING("ssmem", ENCODING_RM)
946 ENCODING("sdmem", ENCODING_RM)
947 ENCODING("f128mem", ENCODING_RM)
948 ENCODING("f256mem", ENCODING_RM)
949 ENCODING("f64mem", ENCODING_RM)
950 ENCODING("f32mem", ENCODING_RM)
951 ENCODING("i128mem", ENCODING_RM)
952 ENCODING("f80mem", ENCODING_RM)
953 ENCODING("lea32mem", ENCODING_RM)
954 ENCODING("lea64_32mem", ENCODING_RM)
955 ENCODING("lea64mem", ENCODING_RM)
956 ENCODING("opaque32mem", ENCODING_RM)
957 ENCODING("opaque48mem", ENCODING_RM)
958 ENCODING("opaque80mem", ENCODING_RM)
959 ENCODING("opaque512mem", ENCODING_RM)
960 errs() << "Unhandled memory encoding " << s << "\n";
961 llvm_unreachable("Unhandled memory encoding");
964 OperandEncoding RecognizableInstr::relocationEncodingFromString
965 (const std::string &s,
966 bool hasOpSizePrefix) {
967 if(!hasOpSizePrefix) {
968 // For instructions without an OpSize prefix, a declared 16-bit register or
969 // immediate encoding is special.
970 ENCODING("i16imm", ENCODING_IW)
972 ENCODING("i16imm", ENCODING_Iv)
973 ENCODING("i16i8imm", ENCODING_IB)
974 ENCODING("i32imm", ENCODING_Iv)
975 ENCODING("i32i8imm", ENCODING_IB)
976 ENCODING("i64i32imm", ENCODING_ID)
977 ENCODING("i64i8imm", ENCODING_IB)
978 ENCODING("i8imm", ENCODING_IB)
979 ENCODING("i64i32imm_pcrel", ENCODING_ID)
980 ENCODING("i16imm_pcrel", ENCODING_IW)
981 ENCODING("i32imm_pcrel", ENCODING_ID)
982 ENCODING("brtarget", ENCODING_Iv)
983 ENCODING("brtarget8", ENCODING_IB)
984 ENCODING("i64imm", ENCODING_IO)
985 ENCODING("offset8", ENCODING_Ia)
986 ENCODING("offset16", ENCODING_Ia)
987 ENCODING("offset32", ENCODING_Ia)
988 ENCODING("offset64", ENCODING_Ia)
989 errs() << "Unhandled relocation encoding " << s << "\n";
990 llvm_unreachable("Unhandled relocation encoding");
993 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
994 (const std::string &s,
995 bool hasOpSizePrefix) {
996 ENCODING("RST", ENCODING_I)
997 ENCODING("GR32", ENCODING_Rv)
998 ENCODING("GR64", ENCODING_RO)
999 ENCODING("GR16", ENCODING_Rv)
1000 ENCODING("GR8", ENCODING_RB)
1001 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1002 llvm_unreachable("Unhandled opcode modifier encoding");