1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
233 SegOvr = byteFromRec(Rec, "SegOvrBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
248 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
249 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
250 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
252 Name = Rec->getName();
253 AsmString = Rec->getValueAsString("AsmString");
255 Operands = &insn.Operands.OperandList;
257 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
258 (Name.find("CRC32") != Name.npos);
259 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
261 // Check for 64-bit inst which does not require REX
264 // FIXME: Is there some better way to check for In64BitMode?
265 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
268 Predicates[i]->getName().find("In32Bit") != Name.npos) {
272 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
277 // FIXME: These instructions aren't marked as 64-bit in any way
278 Is64Bit |= Rec->getName().find("MOV64") != Name.npos ||
279 Rec->getName().find("PUSH64") != Name.npos ||
280 Rec->getName().find("POP64") != Name.npos;
282 ShouldBeEmitted = true;
285 void RecognizableInstr::processInstr(DisassemblerTables &tables,
286 const CodeGenInstruction &insn,
289 // Ignore "asm parser only" instructions.
290 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
293 RecognizableInstr recogInstr(tables, insn, uid);
295 recogInstr.emitInstructionSpecifier();
297 if (recogInstr.shouldBeEmitted())
298 recogInstr.emitDecodePath(tables);
301 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
302 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
303 (HasEVEX_KZ ? n##_KZ : \
304 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
306 InstructionContext RecognizableInstr::insnContext() const {
307 InstructionContext insnContext;
310 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
311 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
312 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
315 if (HasVEX_LPrefix && HasVEX_WPrefix) {
317 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
318 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
319 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
320 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
321 Prefix == X86Local::TAXD)
322 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
324 insnContext = EVEX_KB(IC_EVEX_L_W);
325 } else if (HasVEX_LPrefix) {
328 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
329 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
330 insnContext = EVEX_KB(IC_EVEX_L_XS);
331 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
332 Prefix == X86Local::TAXD)
333 insnContext = EVEX_KB(IC_EVEX_L_XD);
335 insnContext = EVEX_KB(IC_EVEX_L);
337 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
340 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
341 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
342 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
343 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
344 Prefix == X86Local::TAXD)
345 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
347 insnContext = EVEX_KB(IC_EVEX_L2_W);
348 } else if (HasEVEX_L2Prefix) {
351 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
352 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
353 Prefix == X86Local::TAXD)
354 insnContext = EVEX_KB(IC_EVEX_L2_XD);
355 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
356 insnContext = EVEX_KB(IC_EVEX_L2_XS);
358 insnContext = EVEX_KB(IC_EVEX_L2);
360 else if (HasVEX_WPrefix) {
363 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
364 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
365 insnContext = EVEX_KB(IC_EVEX_W_XS);
366 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
367 Prefix == X86Local::TAXD)
368 insnContext = EVEX_KB(IC_EVEX_W_XD);
370 insnContext = EVEX_KB(IC_EVEX_W);
373 else if (HasOpSizePrefix)
374 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
375 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
376 Prefix == X86Local::TAXD)
377 insnContext = EVEX_KB(IC_EVEX_XD);
378 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
379 insnContext = EVEX_KB(IC_EVEX_XS);
381 insnContext = EVEX_KB(IC_EVEX);
383 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
384 if (HasVEX_LPrefix && HasVEX_WPrefix) {
386 insnContext = IC_VEX_L_W_OPSIZE;
387 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
388 insnContext = IC_VEX_L_W_XS;
389 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
390 Prefix == X86Local::TAXD)
391 insnContext = IC_VEX_L_W_XD;
393 insnContext = IC_VEX_L_W;
394 } else if (HasOpSizePrefix && HasVEX_LPrefix)
395 insnContext = IC_VEX_L_OPSIZE;
396 else if (HasOpSizePrefix && HasVEX_WPrefix)
397 insnContext = IC_VEX_W_OPSIZE;
398 else if (HasOpSizePrefix)
399 insnContext = IC_VEX_OPSIZE;
400 else if (HasVEX_LPrefix &&
401 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
402 insnContext = IC_VEX_L_XS;
403 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
404 Prefix == X86Local::T8XD ||
405 Prefix == X86Local::TAXD))
406 insnContext = IC_VEX_L_XD;
407 else if (HasVEX_WPrefix &&
408 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
409 insnContext = IC_VEX_W_XS;
410 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
411 Prefix == X86Local::T8XD ||
412 Prefix == X86Local::TAXD))
413 insnContext = IC_VEX_W_XD;
414 else if (HasVEX_WPrefix)
415 insnContext = IC_VEX_W;
416 else if (HasVEX_LPrefix)
417 insnContext = IC_VEX_L;
418 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
419 Prefix == X86Local::TAXD)
420 insnContext = IC_VEX_XD;
421 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
422 insnContext = IC_VEX_XS;
424 insnContext = IC_VEX;
425 } else if (Is64Bit || HasREX_WPrefix) {
426 if (HasREX_WPrefix && HasOpSizePrefix)
427 insnContext = IC_64BIT_REXW_OPSIZE;
428 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
429 Prefix == X86Local::T8XD ||
430 Prefix == X86Local::TAXD))
431 insnContext = IC_64BIT_XD_OPSIZE;
432 else if (HasOpSizePrefix &&
433 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
434 insnContext = IC_64BIT_XS_OPSIZE;
435 else if (HasOpSizePrefix)
436 insnContext = IC_64BIT_OPSIZE;
437 else if (HasAdSizePrefix)
438 insnContext = IC_64BIT_ADSIZE;
439 else if (HasREX_WPrefix &&
440 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
441 insnContext = IC_64BIT_REXW_XS;
442 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
443 Prefix == X86Local::T8XD ||
444 Prefix == X86Local::TAXD))
445 insnContext = IC_64BIT_REXW_XD;
446 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
447 Prefix == X86Local::TAXD)
448 insnContext = IC_64BIT_XD;
449 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
450 insnContext = IC_64BIT_XS;
451 else if (HasREX_WPrefix)
452 insnContext = IC_64BIT_REXW;
454 insnContext = IC_64BIT;
456 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
457 Prefix == X86Local::T8XD ||
458 Prefix == X86Local::TAXD))
459 insnContext = IC_XD_OPSIZE;
460 else if (HasOpSizePrefix &&
461 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
462 insnContext = IC_XS_OPSIZE;
463 else if (HasOpSizePrefix)
464 insnContext = IC_OPSIZE;
465 else if (HasAdSizePrefix)
466 insnContext = IC_ADSIZE;
467 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
468 Prefix == X86Local::TAXD)
470 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
471 Prefix == X86Local::REP)
480 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
485 // Filter out intrinsics
487 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
489 if (Form == X86Local::Pseudo ||
490 (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
491 Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
492 return FILTER_STRONG;
495 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
496 // printed as a separate "instruction".
498 // Filter out instructions with segment override prefixes.
499 // They're too messy to handle now and we'll special case them if needed.
502 return FILTER_STRONG;
510 // Filter out instructions with a LOCK prefix;
511 // prefer forms that do not have the prefix
515 // Filter out alternate forms of AVX instructions
516 if (Name.find("_alt") != Name.npos ||
517 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
518 Name.find("_64mr") != Name.npos ||
519 Name.find("rr64") != Name.npos)
524 if (Name == "PUSH64i16" ||
525 Name == "MOVPQI2QImr" ||
526 Name == "VMOVPQI2QImr" ||
527 Name == "VMASKMOVDQU64")
530 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
531 // For now, just prefer the REP versions.
532 if (Name == "XACQUIRE_PREFIX" ||
533 Name == "XRELEASE_PREFIX")
536 return FILTER_NORMAL;
539 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
540 unsigned &physicalOperandIndex,
541 unsigned &numPhysicalOperands,
542 const unsigned *operandMapping,
543 OperandEncoding (*encodingFromString)
545 bool hasOpSizePrefix)) {
547 if (physicalOperandIndex >= numPhysicalOperands)
550 assert(physicalOperandIndex < numPhysicalOperands);
553 while (operandMapping[operandIndex] != operandIndex) {
554 Spec->operands[operandIndex].encoding = ENCODING_DUP;
555 Spec->operands[operandIndex].type =
556 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
560 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
562 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
564 Spec->operands[operandIndex].type = typeFromString(typeName,
570 ++physicalOperandIndex;
573 void RecognizableInstr::emitInstructionSpecifier() {
576 if (!ShouldBeEmitted)
581 Spec->filtered = true;
584 ShouldBeEmitted = false;
590 Spec->insnContext = insnContext();
592 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
594 unsigned numOperands = OperandList.size();
595 unsigned numPhysicalOperands = 0;
597 // operandMapping maps from operands in OperandList to their originals.
598 // If operandMapping[i] != i, then the entry is a duplicate.
599 unsigned operandMapping[X86_MAX_OPERANDS];
600 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
602 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
603 if (OperandList[operandIndex].Constraints.size()) {
604 const CGIOperandList::ConstraintInfo &Constraint =
605 OperandList[operandIndex].Constraints[0];
606 if (Constraint.isTied()) {
607 operandMapping[operandIndex] = operandIndex;
608 operandMapping[Constraint.getTiedOperand()] = operandIndex;
610 ++numPhysicalOperands;
611 operandMapping[operandIndex] = operandIndex;
614 ++numPhysicalOperands;
615 operandMapping[operandIndex] = operandIndex;
619 #define HANDLE_OPERAND(class) \
620 handleOperand(false, \
622 physicalOperandIndex, \
623 numPhysicalOperands, \
625 class##EncodingFromString);
627 #define HANDLE_OPTIONAL(class) \
628 handleOperand(true, \
630 physicalOperandIndex, \
631 numPhysicalOperands, \
633 class##EncodingFromString);
635 // operandIndex should always be < numOperands
636 unsigned operandIndex = 0;
637 // physicalOperandIndex should always be < numPhysicalOperands
638 unsigned physicalOperandIndex = 0;
641 case X86Local::RawFrm:
642 // Operand 1 (optional) is an address or immediate.
643 // Operand 2 (optional) is an immediate.
644 assert(numPhysicalOperands <= 2 &&
645 "Unexpected number of operands for RawFrm");
646 HANDLE_OPTIONAL(relocation)
647 HANDLE_OPTIONAL(immediate)
649 case X86Local::AddRegFrm:
650 // Operand 1 is added to the opcode.
651 // Operand 2 (optional) is an address.
652 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
653 "Unexpected number of operands for AddRegFrm");
654 HANDLE_OPERAND(opcodeModifier)
655 HANDLE_OPTIONAL(relocation)
657 case X86Local::MRMDestReg:
658 // Operand 1 is a register operand in the R/M field.
659 // Operand 2 is a register operand in the Reg/Opcode field.
660 // - In AVX, there is a register operand in the VEX.vvvv field here -
661 // Operand 3 (optional) is an immediate.
663 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
664 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
666 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
667 "Unexpected number of operands for MRMDestRegFrm");
669 HANDLE_OPERAND(rmRegister)
672 // FIXME: In AVX, the register below becomes the one encoded
673 // in ModRMVEX and the one above the one in the VEX.VVVV field
674 HANDLE_OPERAND(vvvvRegister)
676 HANDLE_OPERAND(roRegister)
677 HANDLE_OPTIONAL(immediate)
679 case X86Local::MRMDestMem:
680 // Operand 1 is a memory operand (possibly SIB-extended)
681 // Operand 2 is a register operand in the Reg/Opcode field.
682 // - In AVX, there is a register operand in the VEX.vvvv field here -
683 // Operand 3 (optional) is an immediate.
685 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
686 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
688 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
689 "Unexpected number of operands for MRMDestMemFrm");
690 HANDLE_OPERAND(memory)
693 HANDLE_OPERAND(writemaskRegister)
696 // FIXME: In AVX, the register below becomes the one encoded
697 // in ModRMVEX and the one above the one in the VEX.VVVV field
698 HANDLE_OPERAND(vvvvRegister)
700 HANDLE_OPERAND(roRegister)
701 HANDLE_OPTIONAL(immediate)
703 case X86Local::MRMSrcReg:
704 // Operand 1 is a register operand in the Reg/Opcode field.
705 // Operand 2 is a register operand in the R/M field.
706 // - In AVX, there is a register operand in the VEX.vvvv field here -
707 // Operand 3 (optional) is an immediate.
708 // Operand 4 (optional) is an immediate.
710 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
711 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
712 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
714 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
715 "Unexpected number of operands for MRMSrcRegFrm");
717 HANDLE_OPERAND(roRegister)
720 HANDLE_OPERAND(writemaskRegister)
723 // FIXME: In AVX, the register below becomes the one encoded
724 // in ModRMVEX and the one above the one in the VEX.VVVV field
725 HANDLE_OPERAND(vvvvRegister)
728 HANDLE_OPERAND(immediate)
730 HANDLE_OPERAND(rmRegister)
732 if (HasVEX_4VOp3Prefix)
733 HANDLE_OPERAND(vvvvRegister)
735 if (!HasMemOp4Prefix)
736 HANDLE_OPTIONAL(immediate)
737 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
738 HANDLE_OPTIONAL(immediate)
740 case X86Local::MRMSrcMem:
741 // Operand 1 is a register operand in the Reg/Opcode field.
742 // Operand 2 is a memory operand (possibly SIB-extended)
743 // - In AVX, there is a register operand in the VEX.vvvv field here -
744 // Operand 3 (optional) is an immediate.
746 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
747 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
748 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
750 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
751 "Unexpected number of operands for MRMSrcMemFrm");
753 HANDLE_OPERAND(roRegister)
756 HANDLE_OPERAND(writemaskRegister)
759 // FIXME: In AVX, the register below becomes the one encoded
760 // in ModRMVEX and the one above the one in the VEX.VVVV field
761 HANDLE_OPERAND(vvvvRegister)
764 HANDLE_OPERAND(immediate)
766 HANDLE_OPERAND(memory)
768 if (HasVEX_4VOp3Prefix)
769 HANDLE_OPERAND(vvvvRegister)
771 if (!HasMemOp4Prefix)
772 HANDLE_OPTIONAL(immediate)
773 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
775 case X86Local::MRM0r:
776 case X86Local::MRM1r:
777 case X86Local::MRM2r:
778 case X86Local::MRM3r:
779 case X86Local::MRM4r:
780 case X86Local::MRM5r:
781 case X86Local::MRM6r:
782 case X86Local::MRM7r:
784 // Operand 1 is a register operand in the R/M field.
785 // Operand 2 (optional) is an immediate or relocation.
786 // Operand 3 (optional) is an immediate.
787 unsigned kOp = (HasEVEX_K) ? 1:0;
788 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
789 if (numPhysicalOperands > 3 + kOp + Op4v)
790 llvm_unreachable("Unexpected number of operands for MRMnr");
793 HANDLE_OPERAND(vvvvRegister)
796 HANDLE_OPERAND(writemaskRegister)
797 HANDLE_OPTIONAL(rmRegister)
798 HANDLE_OPTIONAL(relocation)
799 HANDLE_OPTIONAL(immediate)
801 case X86Local::MRM0m:
802 case X86Local::MRM1m:
803 case X86Local::MRM2m:
804 case X86Local::MRM3m:
805 case X86Local::MRM4m:
806 case X86Local::MRM5m:
807 case X86Local::MRM6m:
808 case X86Local::MRM7m:
810 // Operand 1 is a memory operand (possibly SIB-extended)
811 // Operand 2 (optional) is an immediate or relocation.
812 unsigned kOp = (HasEVEX_K) ? 1:0;
813 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
814 if (numPhysicalOperands < 1 + kOp + Op4v ||
815 numPhysicalOperands > 2 + kOp + Op4v)
816 llvm_unreachable("Unexpected number of operands for MRMnm");
819 HANDLE_OPERAND(vvvvRegister)
821 HANDLE_OPERAND(writemaskRegister)
822 HANDLE_OPERAND(memory)
823 HANDLE_OPTIONAL(relocation)
825 case X86Local::RawFrmImm8:
826 // operand 1 is a 16-bit immediate
827 // operand 2 is an 8-bit immediate
828 assert(numPhysicalOperands == 2 &&
829 "Unexpected number of operands for X86Local::RawFrmImm8");
830 HANDLE_OPERAND(immediate)
831 HANDLE_OPERAND(immediate)
833 case X86Local::RawFrmImm16:
834 // operand 1 is a 16-bit immediate
835 // operand 2 is a 16-bit immediate
836 HANDLE_OPERAND(immediate)
837 HANDLE_OPERAND(immediate)
839 case X86Local::MRM_F8:
840 if (Opcode == 0xc6) {
841 assert(numPhysicalOperands == 1 &&
842 "Unexpected number of operands for X86Local::MRM_F8");
843 HANDLE_OPERAND(immediate)
844 } else if (Opcode == 0xc7) {
845 assert(numPhysicalOperands == 1 &&
846 "Unexpected number of operands for X86Local::MRM_F8");
847 HANDLE_OPERAND(relocation)
850 case X86Local::MRMInitReg:
855 #undef HANDLE_OPERAND
856 #undef HANDLE_OPTIONAL
859 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
860 // Special cases where the LLVM tables are not complete
862 #define MAP(from, to) \
863 case X86Local::MRM_##from: \
864 filter = new ExactFilter(0x##from); \
867 OpcodeType opcodeType = (OpcodeType)-1;
869 ModRMFilter* filter = NULL;
870 uint8_t opcodeToSet = 0;
873 default: llvm_unreachable("Invalid prefix!");
874 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
878 opcodeType = TWOBYTE;
882 if (needsModRMForDecode(Form))
883 filter = new ModFilter(isRegFormat(Form));
885 filter = new DumbFilter();
887 #define EXTENSION_TABLE(n) case 0x##n:
888 TWO_BYTE_EXTENSION_TABLES
889 #undef EXTENSION_TABLE
892 llvm_unreachable("Unhandled two-byte extended opcode");
893 case X86Local::MRM0r:
894 case X86Local::MRM1r:
895 case X86Local::MRM2r:
896 case X86Local::MRM3r:
897 case X86Local::MRM4r:
898 case X86Local::MRM5r:
899 case X86Local::MRM6r:
900 case X86Local::MRM7r:
901 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
903 case X86Local::MRM0m:
904 case X86Local::MRM1m:
905 case X86Local::MRM2m:
906 case X86Local::MRM3m:
907 case X86Local::MRM4m:
908 case X86Local::MRM5m:
909 case X86Local::MRM6m:
910 case X86Local::MRM7m:
911 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
917 opcodeToSet = Opcode;
922 opcodeType = THREEBYTE_38;
925 if (needsModRMForDecode(Form))
926 filter = new ModFilter(isRegFormat(Form));
928 filter = new DumbFilter();
930 #define EXTENSION_TABLE(n) case 0x##n:
931 THREE_BYTE_38_EXTENSION_TABLES
932 #undef EXTENSION_TABLE
935 llvm_unreachable("Unhandled two-byte extended opcode");
936 case X86Local::MRM0r:
937 case X86Local::MRM1r:
938 case X86Local::MRM2r:
939 case X86Local::MRM3r:
940 case X86Local::MRM4r:
941 case X86Local::MRM5r:
942 case X86Local::MRM6r:
943 case X86Local::MRM7r:
944 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
946 case X86Local::MRM0m:
947 case X86Local::MRM1m:
948 case X86Local::MRM2m:
949 case X86Local::MRM3m:
950 case X86Local::MRM4m:
951 case X86Local::MRM5m:
952 case X86Local::MRM6m:
953 case X86Local::MRM7m:
954 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
960 opcodeToSet = Opcode;
964 opcodeType = THREEBYTE_3A;
965 if (needsModRMForDecode(Form))
966 filter = new ModFilter(isRegFormat(Form));
968 filter = new DumbFilter();
969 opcodeToSet = Opcode;
972 opcodeType = THREEBYTE_A6;
973 if (needsModRMForDecode(Form))
974 filter = new ModFilter(isRegFormat(Form));
976 filter = new DumbFilter();
977 opcodeToSet = Opcode;
980 opcodeType = THREEBYTE_A7;
981 if (needsModRMForDecode(Form))
982 filter = new ModFilter(isRegFormat(Form));
984 filter = new DumbFilter();
985 opcodeToSet = Opcode;
988 opcodeType = XOP8_MAP;
989 if (needsModRMForDecode(Form))
990 filter = new ModFilter(isRegFormat(Form));
992 filter = new DumbFilter();
993 opcodeToSet = Opcode;
996 opcodeType = XOP9_MAP;
999 if (needsModRMForDecode(Form))
1000 filter = new ModFilter(isRegFormat(Form));
1002 filter = new DumbFilter();
1004 #define EXTENSION_TABLE(n) case 0x##n:
1005 XOP9_MAP_EXTENSION_TABLES
1006 #undef EXTENSION_TABLE
1009 llvm_unreachable("Unhandled XOP9 extended opcode");
1010 case X86Local::MRM0r:
1011 case X86Local::MRM1r:
1012 case X86Local::MRM2r:
1013 case X86Local::MRM3r:
1014 case X86Local::MRM4r:
1015 case X86Local::MRM5r:
1016 case X86Local::MRM6r:
1017 case X86Local::MRM7r:
1018 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1020 case X86Local::MRM0m:
1021 case X86Local::MRM1m:
1022 case X86Local::MRM2m:
1023 case X86Local::MRM3m:
1024 case X86Local::MRM4m:
1025 case X86Local::MRM5m:
1026 case X86Local::MRM6m:
1027 case X86Local::MRM7m:
1028 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1033 } // switch (Opcode)
1034 opcodeToSet = Opcode;
1036 case X86Local::XOPA:
1037 opcodeType = XOPA_MAP;
1038 if (needsModRMForDecode(Form))
1039 filter = new ModFilter(isRegFormat(Form));
1041 filter = new DumbFilter();
1042 opcodeToSet = Opcode;
1052 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1053 assert(Form == X86Local::RawFrm);
1054 opcodeType = ONEBYTE;
1055 filter = new ExactFilter(Opcode);
1056 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1060 opcodeType = ONEBYTE;
1062 #define EXTENSION_TABLE(n) case 0x##n:
1063 ONE_BYTE_EXTENSION_TABLES
1064 #undef EXTENSION_TABLE
1067 llvm_unreachable("Fell through the cracks of a single-byte "
1069 case X86Local::MRM0r:
1070 case X86Local::MRM1r:
1071 case X86Local::MRM2r:
1072 case X86Local::MRM3r:
1073 case X86Local::MRM4r:
1074 case X86Local::MRM5r:
1075 case X86Local::MRM6r:
1076 case X86Local::MRM7r:
1077 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1079 case X86Local::MRM0m:
1080 case X86Local::MRM1m:
1081 case X86Local::MRM2m:
1082 case X86Local::MRM3m:
1083 case X86Local::MRM4m:
1084 case X86Local::MRM5m:
1085 case X86Local::MRM6m:
1086 case X86Local::MRM7m:
1087 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1102 llvm_unreachable("Unhandled escape opcode form");
1103 case X86Local::MRM0r:
1104 case X86Local::MRM1r:
1105 case X86Local::MRM2r:
1106 case X86Local::MRM3r:
1107 case X86Local::MRM4r:
1108 case X86Local::MRM5r:
1109 case X86Local::MRM6r:
1110 case X86Local::MRM7r:
1111 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1113 case X86Local::MRM0m:
1114 case X86Local::MRM1m:
1115 case X86Local::MRM2m:
1116 case X86Local::MRM3m:
1117 case X86Local::MRM4m:
1118 case X86Local::MRM5m:
1119 case X86Local::MRM6m:
1120 case X86Local::MRM7m:
1121 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1126 if (needsModRMForDecode(Form))
1127 filter = new ModFilter(isRegFormat(Form));
1129 filter = new DumbFilter();
1131 } // switch (Opcode)
1132 opcodeToSet = Opcode;
1133 } // switch (Prefix)
1135 assert(opcodeType != (OpcodeType)-1 &&
1136 "Opcode type not set");
1137 assert(filter && "Filter not set");
1139 if (Form == X86Local::AddRegFrm) {
1140 assert(((opcodeToSet & 7) == 0) &&
1141 "ADDREG_FRM opcode not aligned");
1143 uint8_t currentOpcode;
1145 for (currentOpcode = opcodeToSet;
1146 currentOpcode < opcodeToSet + 8;
1148 tables.setTableFields(opcodeType,
1152 UID, Is32Bit, IgnoresVEX_L);
1154 tables.setTableFields(opcodeType,
1158 UID, Is32Bit, IgnoresVEX_L);
1166 #define TYPE(str, type) if (s == str) return type;
1167 OperandType RecognizableInstr::typeFromString(const std::string &s,
1169 bool hasREX_WPrefix,
1170 bool hasOpSizePrefix) {
1172 // For SSE instructions, we ignore the OpSize prefix and force operand
1174 TYPE("GR16", TYPE_R16)
1175 TYPE("GR32", TYPE_R32)
1176 TYPE("GR64", TYPE_R64)
1178 if(hasREX_WPrefix) {
1179 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1181 TYPE("GR32", TYPE_R32)
1183 if(!hasOpSizePrefix) {
1184 // For instructions without an OpSize prefix, a declared 16-bit register or
1185 // immediate encoding is special.
1186 TYPE("GR16", TYPE_R16)
1187 TYPE("i16imm", TYPE_IMM16)
1189 TYPE("i16mem", TYPE_Mv)
1190 TYPE("i16imm", TYPE_IMMv)
1191 TYPE("i16i8imm", TYPE_IMMv)
1192 TYPE("GR16", TYPE_Rv)
1193 TYPE("i32mem", TYPE_Mv)
1194 TYPE("i32imm", TYPE_IMMv)
1195 TYPE("i32i8imm", TYPE_IMM32)
1196 TYPE("u32u8imm", TYPE_IMM32)
1197 TYPE("GR32", TYPE_Rv)
1198 TYPE("GR32orGR64", TYPE_R32)
1199 TYPE("i64mem", TYPE_Mv)
1200 TYPE("i64i32imm", TYPE_IMM64)
1201 TYPE("i64i8imm", TYPE_IMM64)
1202 TYPE("GR64", TYPE_R64)
1203 TYPE("i8mem", TYPE_M8)
1204 TYPE("i8imm", TYPE_IMM8)
1205 TYPE("GR8", TYPE_R8)
1206 TYPE("VR128", TYPE_XMM128)
1207 TYPE("VR128X", TYPE_XMM128)
1208 TYPE("f128mem", TYPE_M128)
1209 TYPE("f256mem", TYPE_M256)
1210 TYPE("f512mem", TYPE_M512)
1211 TYPE("FR64", TYPE_XMM64)
1212 TYPE("FR64X", TYPE_XMM64)
1213 TYPE("f64mem", TYPE_M64FP)
1214 TYPE("sdmem", TYPE_M64FP)
1215 TYPE("FR32", TYPE_XMM32)
1216 TYPE("FR32X", TYPE_XMM32)
1217 TYPE("f32mem", TYPE_M32FP)
1218 TYPE("ssmem", TYPE_M32FP)
1219 TYPE("RST", TYPE_ST)
1220 TYPE("i128mem", TYPE_M128)
1221 TYPE("i256mem", TYPE_M256)
1222 TYPE("i512mem", TYPE_M512)
1223 TYPE("i64i32imm_pcrel", TYPE_REL64)
1224 TYPE("i16imm_pcrel", TYPE_REL16)
1225 TYPE("i32imm_pcrel", TYPE_REL32)
1226 TYPE("SSECC", TYPE_IMM3)
1227 TYPE("AVXCC", TYPE_IMM5)
1228 TYPE("AVX512RC", TYPE_IMM32)
1229 TYPE("brtarget", TYPE_RELv)
1230 TYPE("uncondbrtarget", TYPE_RELv)
1231 TYPE("brtarget8", TYPE_REL8)
1232 TYPE("f80mem", TYPE_M80FP)
1233 TYPE("lea32mem", TYPE_LEA)
1234 TYPE("lea64_32mem", TYPE_LEA)
1235 TYPE("lea64mem", TYPE_LEA)
1236 TYPE("VR64", TYPE_MM64)
1237 TYPE("i64imm", TYPE_IMMv)
1238 TYPE("opaque32mem", TYPE_M1616)
1239 TYPE("opaque48mem", TYPE_M1632)
1240 TYPE("opaque80mem", TYPE_M1664)
1241 TYPE("opaque512mem", TYPE_M512)
1242 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1243 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1244 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1245 TYPE("offset8", TYPE_MOFFS8)
1246 TYPE("offset16", TYPE_MOFFS16)
1247 TYPE("offset32", TYPE_MOFFS32)
1248 TYPE("offset64", TYPE_MOFFS64)
1249 TYPE("VR256", TYPE_XMM256)
1250 TYPE("VR256X", TYPE_XMM256)
1251 TYPE("VR512", TYPE_XMM512)
1252 TYPE("VK1", TYPE_VK1)
1253 TYPE("VK1WM", TYPE_VK1)
1254 TYPE("VK8", TYPE_VK8)
1255 TYPE("VK8WM", TYPE_VK8)
1256 TYPE("VK16", TYPE_VK16)
1257 TYPE("VK16WM", TYPE_VK16)
1258 TYPE("GR16_NOAX", TYPE_Rv)
1259 TYPE("GR32_NOAX", TYPE_Rv)
1260 TYPE("GR64_NOAX", TYPE_R64)
1261 TYPE("vx32mem", TYPE_M32)
1262 TYPE("vy32mem", TYPE_M32)
1263 TYPE("vz32mem", TYPE_M32)
1264 TYPE("vx64mem", TYPE_M64)
1265 TYPE("vy64mem", TYPE_M64)
1266 TYPE("vy64xmem", TYPE_M64)
1267 TYPE("vz64mem", TYPE_M64)
1268 errs() << "Unhandled type string " << s << "\n";
1269 llvm_unreachable("Unhandled type string");
1273 #define ENCODING(str, encoding) if (s == str) return encoding;
1274 OperandEncoding RecognizableInstr::immediateEncodingFromString
1275 (const std::string &s,
1276 bool hasOpSizePrefix) {
1277 if(!hasOpSizePrefix) {
1278 // For instructions without an OpSize prefix, a declared 16-bit register or
1279 // immediate encoding is special.
1280 ENCODING("i16imm", ENCODING_IW)
1282 ENCODING("i32i8imm", ENCODING_IB)
1283 ENCODING("u32u8imm", ENCODING_IB)
1284 ENCODING("SSECC", ENCODING_IB)
1285 ENCODING("AVXCC", ENCODING_IB)
1286 ENCODING("AVX512RC", ENCODING_IB)
1287 ENCODING("i16imm", ENCODING_Iv)
1288 ENCODING("i16i8imm", ENCODING_IB)
1289 ENCODING("i32imm", ENCODING_Iv)
1290 ENCODING("i64i32imm", ENCODING_ID)
1291 ENCODING("i64i8imm", ENCODING_IB)
1292 ENCODING("i8imm", ENCODING_IB)
1293 // This is not a typo. Instructions like BLENDVPD put
1294 // register IDs in 8-bit immediates nowadays.
1295 ENCODING("FR32", ENCODING_IB)
1296 ENCODING("FR64", ENCODING_IB)
1297 ENCODING("VR128", ENCODING_IB)
1298 ENCODING("VR256", ENCODING_IB)
1299 ENCODING("FR32X", ENCODING_IB)
1300 ENCODING("FR64X", ENCODING_IB)
1301 ENCODING("VR128X", ENCODING_IB)
1302 ENCODING("VR256X", ENCODING_IB)
1303 ENCODING("VR512", ENCODING_IB)
1304 errs() << "Unhandled immediate encoding " << s << "\n";
1305 llvm_unreachable("Unhandled immediate encoding");
1308 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1309 (const std::string &s,
1310 bool hasOpSizePrefix) {
1311 ENCODING("RST", ENCODING_FP)
1312 ENCODING("GR16", ENCODING_RM)
1313 ENCODING("GR32", ENCODING_RM)
1314 ENCODING("GR32orGR64", ENCODING_RM)
1315 ENCODING("GR64", ENCODING_RM)
1316 ENCODING("GR8", ENCODING_RM)
1317 ENCODING("VR128", ENCODING_RM)
1318 ENCODING("VR128X", ENCODING_RM)
1319 ENCODING("FR64", ENCODING_RM)
1320 ENCODING("FR32", ENCODING_RM)
1321 ENCODING("FR64X", ENCODING_RM)
1322 ENCODING("FR32X", ENCODING_RM)
1323 ENCODING("VR64", ENCODING_RM)
1324 ENCODING("VR256", ENCODING_RM)
1325 ENCODING("VR256X", ENCODING_RM)
1326 ENCODING("VR512", ENCODING_RM)
1327 ENCODING("VK1", ENCODING_RM)
1328 ENCODING("VK8", ENCODING_RM)
1329 ENCODING("VK16", ENCODING_RM)
1330 errs() << "Unhandled R/M register encoding " << s << "\n";
1331 llvm_unreachable("Unhandled R/M register encoding");
1334 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1335 (const std::string &s,
1336 bool hasOpSizePrefix) {
1337 ENCODING("GR16", ENCODING_REG)
1338 ENCODING("GR32", ENCODING_REG)
1339 ENCODING("GR32orGR64", ENCODING_REG)
1340 ENCODING("GR64", ENCODING_REG)
1341 ENCODING("GR8", ENCODING_REG)
1342 ENCODING("VR128", ENCODING_REG)
1343 ENCODING("FR64", ENCODING_REG)
1344 ENCODING("FR32", ENCODING_REG)
1345 ENCODING("VR64", ENCODING_REG)
1346 ENCODING("SEGMENT_REG", ENCODING_REG)
1347 ENCODING("DEBUG_REG", ENCODING_REG)
1348 ENCODING("CONTROL_REG", ENCODING_REG)
1349 ENCODING("VR256", ENCODING_REG)
1350 ENCODING("VR256X", ENCODING_REG)
1351 ENCODING("VR128X", ENCODING_REG)
1352 ENCODING("FR64X", ENCODING_REG)
1353 ENCODING("FR32X", ENCODING_REG)
1354 ENCODING("VR512", ENCODING_REG)
1355 ENCODING("VK1", ENCODING_REG)
1356 ENCODING("VK8", ENCODING_REG)
1357 ENCODING("VK16", ENCODING_REG)
1358 ENCODING("VK1WM", ENCODING_REG)
1359 ENCODING("VK8WM", ENCODING_REG)
1360 ENCODING("VK16WM", ENCODING_REG)
1361 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1362 llvm_unreachable("Unhandled reg/opcode register encoding");
1365 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1366 (const std::string &s,
1367 bool hasOpSizePrefix) {
1368 ENCODING("GR32", ENCODING_VVVV)
1369 ENCODING("GR64", ENCODING_VVVV)
1370 ENCODING("FR32", ENCODING_VVVV)
1371 ENCODING("FR64", ENCODING_VVVV)
1372 ENCODING("VR128", ENCODING_VVVV)
1373 ENCODING("VR256", ENCODING_VVVV)
1374 ENCODING("FR32X", ENCODING_VVVV)
1375 ENCODING("FR64X", ENCODING_VVVV)
1376 ENCODING("VR128X", ENCODING_VVVV)
1377 ENCODING("VR256X", ENCODING_VVVV)
1378 ENCODING("VR512", ENCODING_VVVV)
1379 ENCODING("VK1", ENCODING_VVVV)
1380 ENCODING("VK8", ENCODING_VVVV)
1381 ENCODING("VK16", ENCODING_VVVV)
1382 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1383 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1386 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1387 (const std::string &s,
1388 bool hasOpSizePrefix) {
1389 ENCODING("VK1WM", ENCODING_WRITEMASK)
1390 ENCODING("VK8WM", ENCODING_WRITEMASK)
1391 ENCODING("VK16WM", ENCODING_WRITEMASK)
1392 errs() << "Unhandled mask register encoding " << s << "\n";
1393 llvm_unreachable("Unhandled mask register encoding");
1396 OperandEncoding RecognizableInstr::memoryEncodingFromString
1397 (const std::string &s,
1398 bool hasOpSizePrefix) {
1399 ENCODING("i16mem", ENCODING_RM)
1400 ENCODING("i32mem", ENCODING_RM)
1401 ENCODING("i64mem", ENCODING_RM)
1402 ENCODING("i8mem", ENCODING_RM)
1403 ENCODING("ssmem", ENCODING_RM)
1404 ENCODING("sdmem", ENCODING_RM)
1405 ENCODING("f128mem", ENCODING_RM)
1406 ENCODING("f256mem", ENCODING_RM)
1407 ENCODING("f512mem", ENCODING_RM)
1408 ENCODING("f64mem", ENCODING_RM)
1409 ENCODING("f32mem", ENCODING_RM)
1410 ENCODING("i128mem", ENCODING_RM)
1411 ENCODING("i256mem", ENCODING_RM)
1412 ENCODING("i512mem", ENCODING_RM)
1413 ENCODING("f80mem", ENCODING_RM)
1414 ENCODING("lea32mem", ENCODING_RM)
1415 ENCODING("lea64_32mem", ENCODING_RM)
1416 ENCODING("lea64mem", ENCODING_RM)
1417 ENCODING("opaque32mem", ENCODING_RM)
1418 ENCODING("opaque48mem", ENCODING_RM)
1419 ENCODING("opaque80mem", ENCODING_RM)
1420 ENCODING("opaque512mem", ENCODING_RM)
1421 ENCODING("vx32mem", ENCODING_RM)
1422 ENCODING("vy32mem", ENCODING_RM)
1423 ENCODING("vz32mem", ENCODING_RM)
1424 ENCODING("vx64mem", ENCODING_RM)
1425 ENCODING("vy64mem", ENCODING_RM)
1426 ENCODING("vy64xmem", ENCODING_RM)
1427 ENCODING("vz64mem", ENCODING_RM)
1428 errs() << "Unhandled memory encoding " << s << "\n";
1429 llvm_unreachable("Unhandled memory encoding");
1432 OperandEncoding RecognizableInstr::relocationEncodingFromString
1433 (const std::string &s,
1434 bool hasOpSizePrefix) {
1435 if(!hasOpSizePrefix) {
1436 // For instructions without an OpSize prefix, a declared 16-bit register or
1437 // immediate encoding is special.
1438 ENCODING("i16imm", ENCODING_IW)
1440 ENCODING("i16imm", ENCODING_Iv)
1441 ENCODING("i16i8imm", ENCODING_IB)
1442 ENCODING("i32imm", ENCODING_Iv)
1443 ENCODING("i32i8imm", ENCODING_IB)
1444 ENCODING("i64i32imm", ENCODING_ID)
1445 ENCODING("i64i8imm", ENCODING_IB)
1446 ENCODING("i8imm", ENCODING_IB)
1447 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1448 ENCODING("i16imm_pcrel", ENCODING_IW)
1449 ENCODING("i32imm_pcrel", ENCODING_ID)
1450 ENCODING("brtarget", ENCODING_Iv)
1451 ENCODING("brtarget8", ENCODING_IB)
1452 ENCODING("i64imm", ENCODING_IO)
1453 ENCODING("offset8", ENCODING_Ia)
1454 ENCODING("offset16", ENCODING_Ia)
1455 ENCODING("offset32", ENCODING_Ia)
1456 ENCODING("offset64", ENCODING_Ia)
1457 errs() << "Unhandled relocation encoding " << s << "\n";
1458 llvm_unreachable("Unhandled relocation encoding");
1461 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1462 (const std::string &s,
1463 bool hasOpSizePrefix) {
1464 ENCODING("GR32", ENCODING_Rv)
1465 ENCODING("GR64", ENCODING_RO)
1466 ENCODING("GR16", ENCODING_Rv)
1467 ENCODING("GR8", ENCODING_RB)
1468 ENCODING("GR16_NOAX", ENCODING_Rv)
1469 ENCODING("GR32_NOAX", ENCODING_Rv)
1470 ENCODING("GR64_NOAX", ENCODING_RO)
1471 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1472 llvm_unreachable("Unhandled opcode modifier encoding");