1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
41 // A clone of X86 since we can't depend on something that is generated.
51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
56 #define MAP(from, to) MRM_##from = to,
67 D8 = 3, D9 = 4, DA = 5, DB = 6,
68 DC = 7, DD = 8, DE = 9, DF = 10,
71 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
92 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(c6) \
101 EXTENSION_TABLE(c7) \
102 EXTENSION_TABLE(d0) \
103 EXTENSION_TABLE(d1) \
104 EXTENSION_TABLE(d2) \
105 EXTENSION_TABLE(d3) \
106 EXTENSION_TABLE(f6) \
107 EXTENSION_TABLE(f7) \
108 EXTENSION_TABLE(fe) \
111 #define TWO_BYTE_EXTENSION_TABLES \
112 EXTENSION_TABLE(00) \
113 EXTENSION_TABLE(01) \
114 EXTENSION_TABLE(18) \
115 EXTENSION_TABLE(71) \
116 EXTENSION_TABLE(72) \
117 EXTENSION_TABLE(73) \
118 EXTENSION_TABLE(ae) \
119 EXTENSION_TABLE(ba) \
122 #define THREE_BYTE_38_EXTENSION_TABLES \
125 using namespace X86Disassembler;
127 /// needsModRMForDecode - Indicates whether a particular instruction requires a
128 /// ModR/M byte for the instruction to be properly decoded. For example, a
129 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
132 /// @param form - The form of the instruction.
133 /// @return - true if the form implies that a ModR/M byte is required, false
135 static bool needsModRMForDecode(uint8_t form) {
136 if (form == X86Local::MRMDestReg ||
137 form == X86Local::MRMDestMem ||
138 form == X86Local::MRMSrcReg ||
139 form == X86Local::MRMSrcMem ||
140 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
141 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
147 /// isRegFormat - Indicates whether a particular form requires the Mod field of
148 /// the ModR/M byte to be 0b11.
150 /// @param form - The form of the instruction.
151 /// @return - true if the form implies that Mod must be 0b11, false
153 static bool isRegFormat(uint8_t form) {
154 if (form == X86Local::MRMDestReg ||
155 form == X86Local::MRMSrcReg ||
156 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
162 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
163 /// Useful for switch statements and the like.
165 /// @param init - A reference to the BitsInit to be decoded.
166 /// @return - The field, with the first bit in the BitsInit as the lowest
168 static uint8_t byteFromBitsInit(BitsInit &init) {
169 int width = init.getNumBits();
171 assert(width <= 8 && "Field is too large for uint8_t!");
178 for (index = 0; index < width; index++) {
179 if (static_cast<BitInit*>(init.getBit(index))->getValue())
188 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
189 /// name of the field.
191 /// @param rec - The record from which to extract the value.
192 /// @param name - The name of the field in the record.
193 /// @return - The field, as translated by byteFromBitsInit().
194 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
195 BitsInit* bits = rec->getValueAsBitsInit(name);
196 return byteFromBitsInit(*bits);
199 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
200 const CodeGenInstruction &insn,
205 Name = Rec->getName();
206 Spec = &tables.specForUID(UID);
208 if (!Rec->isSubClassOf("X86Inst")) {
209 ShouldBeEmitted = false;
213 Prefix = byteFromRec(Rec, "Prefix");
214 Opcode = byteFromRec(Rec, "Opcode");
215 Form = byteFromRec(Rec, "FormBits");
216 SegOvr = byteFromRec(Rec, "SegOvrBits");
218 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
219 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
220 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
221 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
222 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
223 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
224 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
225 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
226 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
228 Name = Rec->getName();
229 AsmString = Rec->getValueAsString("AsmString");
231 Operands = &insn.Operands.OperandList;
233 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
234 (Name.find("CRC32") != Name.npos);
235 HasFROperands = hasFROperands();
236 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
238 // Check for 64-bit inst which does not require REX
241 // FIXME: Is there some better way to check for In64BitMode?
242 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
243 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
244 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
248 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
253 // FIXME: These instructions aren't marked as 64-bit in any way
254 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
255 Rec->getName() == "MASKMOVDQU64" ||
256 Rec->getName() == "POPFS64" ||
257 Rec->getName() == "POPGS64" ||
258 Rec->getName() == "PUSHFS64" ||
259 Rec->getName() == "PUSHGS64" ||
260 Rec->getName() == "REX64_PREFIX" ||
261 Rec->getName().find("MOV64") != Name.npos ||
262 Rec->getName().find("PUSH64") != Name.npos ||
263 Rec->getName().find("POP64") != Name.npos;
265 ShouldBeEmitted = true;
268 void RecognizableInstr::processInstr(DisassemblerTables &tables,
269 const CodeGenInstruction &insn,
272 // Ignore "asm parser only" instructions.
273 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
276 RecognizableInstr recogInstr(tables, insn, uid);
278 recogInstr.emitInstructionSpecifier(tables);
280 if (recogInstr.shouldBeEmitted())
281 recogInstr.emitDecodePath(tables);
284 InstructionContext RecognizableInstr::insnContext() const {
285 InstructionContext insnContext;
287 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
288 if (HasVEX_LPrefix && HasVEX_WPrefix)
289 llvm_unreachable("Don't support VEX.L and VEX.W together");
290 else if (HasOpSizePrefix && HasVEX_LPrefix)
291 insnContext = IC_VEX_L_OPSIZE;
292 else if (HasOpSizePrefix && HasVEX_WPrefix)
293 insnContext = IC_VEX_W_OPSIZE;
294 else if (HasOpSizePrefix)
295 insnContext = IC_VEX_OPSIZE;
296 else if (HasVEX_LPrefix &&
297 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
298 insnContext = IC_VEX_L_XS;
299 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
300 Prefix == X86Local::T8XD ||
301 Prefix == X86Local::TAXD))
302 insnContext = IC_VEX_L_XD;
303 else if (HasVEX_WPrefix &&
304 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
305 insnContext = IC_VEX_W_XS;
306 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
307 Prefix == X86Local::T8XD ||
308 Prefix == X86Local::TAXD))
309 insnContext = IC_VEX_W_XD;
310 else if (HasVEX_WPrefix)
311 insnContext = IC_VEX_W;
312 else if (HasVEX_LPrefix)
313 insnContext = IC_VEX_L;
314 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
315 Prefix == X86Local::TAXD)
316 insnContext = IC_VEX_XD;
317 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
318 insnContext = IC_VEX_XS;
320 insnContext = IC_VEX;
321 } else if (Is64Bit || HasREX_WPrefix) {
322 if (HasREX_WPrefix && HasOpSizePrefix)
323 insnContext = IC_64BIT_REXW_OPSIZE;
324 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
325 Prefix == X86Local::T8XD ||
326 Prefix == X86Local::TAXD))
327 insnContext = IC_64BIT_XD_OPSIZE;
328 else if (HasOpSizePrefix &&
329 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
330 insnContext = IC_64BIT_XS_OPSIZE;
331 else if (HasOpSizePrefix)
332 insnContext = IC_64BIT_OPSIZE;
333 else if (HasREX_WPrefix &&
334 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
335 insnContext = IC_64BIT_REXW_XS;
336 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
337 Prefix == X86Local::T8XD ||
338 Prefix == X86Local::TAXD))
339 insnContext = IC_64BIT_REXW_XD;
340 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
341 Prefix == X86Local::TAXD)
342 insnContext = IC_64BIT_XD;
343 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
344 insnContext = IC_64BIT_XS;
345 else if (HasREX_WPrefix)
346 insnContext = IC_64BIT_REXW;
348 insnContext = IC_64BIT;
350 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
351 Prefix == X86Local::T8XD ||
352 Prefix == X86Local::TAXD))
353 insnContext = IC_XD_OPSIZE;
354 else if (HasOpSizePrefix &&
355 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
356 insnContext = IC_XS_OPSIZE;
357 else if (HasOpSizePrefix)
358 insnContext = IC_OPSIZE;
359 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
360 Prefix == X86Local::TAXD)
362 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
363 Prefix == X86Local::REP)
372 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
377 // Filter out intrinsics
379 if (!Rec->isSubClassOf("X86Inst"))
380 return FILTER_STRONG;
382 if (Form == X86Local::Pseudo ||
383 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
384 return FILTER_STRONG;
386 if (Form == X86Local::MRMInitReg)
387 return FILTER_STRONG;
390 // Filter out artificial instructions
392 if (Name.find("TAILJMP") != Name.npos ||
393 Name.find("_Int") != Name.npos ||
394 Name.find("_int") != Name.npos ||
395 Name.find("Int_") != Name.npos ||
396 Name.find("_NOREX") != Name.npos ||
397 Name.find("_TC") != Name.npos ||
398 Name.find("EH_RETURN") != Name.npos ||
399 Name.find("V_SET") != Name.npos ||
400 Name.find("LOCK_") != Name.npos ||
401 Name.find("WIN") != Name.npos ||
402 Name.find("_AVX") != Name.npos ||
403 Name.find("2SDL") != Name.npos)
404 return FILTER_STRONG;
406 // Filter out instructions with segment override prefixes.
407 // They're too messy to handle now and we'll special case them if needed.
410 return FILTER_STRONG;
412 // Filter out instructions that can't be printed.
414 if (AsmString.size() == 0)
415 return FILTER_STRONG;
417 // Filter out instructions with subreg operands.
419 if (AsmString.find("subreg") != AsmString.npos)
420 return FILTER_STRONG;
427 // Filter out instructions with a LOCK prefix;
428 // prefer forms that do not have the prefix
432 // Filter out alternate forms of AVX instructions
433 if (Name.find("_alt") != Name.npos ||
434 Name.find("XrYr") != Name.npos ||
435 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
436 Name.find("_64mr") != Name.npos ||
437 Name.find("Xrr") != Name.npos ||
438 Name.find("rr64") != Name.npos)
441 if (Name == "VMASKMOVDQU64" ||
442 Name == "VEXTRACTPSrr64" ||
443 Name == "VMOVQd64rr" ||
444 Name == "VMOVQs64rr")
449 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
451 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
454 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
456 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
458 if (Name.find("Fs") != Name.npos)
460 if (Name == "MOVLPDrr" ||
461 Name == "MOVLPSrr" ||
467 Name == "MOVSX16rm8" ||
468 Name == "MOVSX16rr8" ||
469 Name == "MOVZX16rm8" ||
470 Name == "MOVZX16rr8" ||
471 Name == "PUSH32i16" ||
472 Name == "PUSH64i16" ||
473 Name == "MOVPQI2QImr" ||
474 Name == "VMOVPQI2QImr" ||
479 Name == "MMX_MOVD64rrv164" ||
480 Name == "CRC32m16" ||
481 Name == "MOV64ri64i32" ||
485 if (HasFROperands && Name.find("MOV") != Name.npos &&
486 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
487 (Name.find("to") != Name.npos)))
490 return FILTER_NORMAL;
493 bool RecognizableInstr::hasFROperands() const {
494 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
495 unsigned numOperands = OperandList.size();
497 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
498 const std::string &recName = OperandList[operandIndex].Rec->getName();
500 if (recName.find("FR") != recName.npos)
506 bool RecognizableInstr::has256BitOperands() const {
507 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
508 unsigned numOperands = OperandList.size();
510 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
511 const std::string &recName = OperandList[operandIndex].Rec->getName();
513 if (!recName.compare("VR256") || !recName.compare("f256mem")) {
520 void RecognizableInstr::handleOperand(
522 unsigned &operandIndex,
523 unsigned &physicalOperandIndex,
524 unsigned &numPhysicalOperands,
525 unsigned *operandMapping,
526 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
528 if (physicalOperandIndex >= numPhysicalOperands)
531 assert(physicalOperandIndex < numPhysicalOperands);
534 while (operandMapping[operandIndex] != operandIndex) {
535 Spec->operands[operandIndex].encoding = ENCODING_DUP;
536 Spec->operands[operandIndex].type =
537 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
541 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
543 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
545 Spec->operands[operandIndex].type = typeFromString(typeName,
551 ++physicalOperandIndex;
554 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
557 if (!Rec->isSubClassOf("X86Inst"))
562 Spec->filtered = true;
565 ShouldBeEmitted = false;
571 Spec->insnContext = insnContext();
573 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
575 unsigned operandIndex;
576 unsigned numOperands = OperandList.size();
577 unsigned numPhysicalOperands = 0;
579 // operandMapping maps from operands in OperandList to their originals.
580 // If operandMapping[i] != i, then the entry is a duplicate.
581 unsigned operandMapping[X86_MAX_OPERANDS];
583 bool hasFROperands = false;
585 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
587 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
588 if (OperandList[operandIndex].Constraints.size()) {
589 const CGIOperandList::ConstraintInfo &Constraint =
590 OperandList[operandIndex].Constraints[0];
591 if (Constraint.isTied()) {
592 operandMapping[operandIndex] = Constraint.getTiedOperand();
594 ++numPhysicalOperands;
595 operandMapping[operandIndex] = operandIndex;
598 ++numPhysicalOperands;
599 operandMapping[operandIndex] = operandIndex;
602 const std::string &recName = OperandList[operandIndex].Rec->getName();
604 if (recName.find("FR") != recName.npos)
605 hasFROperands = true;
608 if (hasFROperands && Name.find("MOV") != Name.npos &&
609 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
610 (Name.find("to") != Name.npos)))
611 ShouldBeEmitted = false;
613 if (!ShouldBeEmitted)
616 #define HANDLE_OPERAND(class) \
617 handleOperand(false, \
619 physicalOperandIndex, \
620 numPhysicalOperands, \
622 class##EncodingFromString);
624 #define HANDLE_OPTIONAL(class) \
625 handleOperand(true, \
627 physicalOperandIndex, \
628 numPhysicalOperands, \
630 class##EncodingFromString);
632 // operandIndex should always be < numOperands
634 // physicalOperandIndex should always be < numPhysicalOperands
635 unsigned physicalOperandIndex = 0;
638 case X86Local::RawFrm:
639 // Operand 1 (optional) is an address or immediate.
640 // Operand 2 (optional) is an immediate.
641 assert(numPhysicalOperands <= 2 &&
642 "Unexpected number of operands for RawFrm");
643 HANDLE_OPTIONAL(relocation)
644 HANDLE_OPTIONAL(immediate)
646 case X86Local::AddRegFrm:
647 // Operand 1 is added to the opcode.
648 // Operand 2 (optional) is an address.
649 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
650 "Unexpected number of operands for AddRegFrm");
651 HANDLE_OPERAND(opcodeModifier)
652 HANDLE_OPTIONAL(relocation)
654 case X86Local::MRMDestReg:
655 // Operand 1 is a register operand in the R/M field.
656 // Operand 2 is a register operand in the Reg/Opcode field.
657 // - In AVX, there is a register operand in the VEX.vvvv field here -
658 // Operand 3 (optional) is an immediate.
660 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
661 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
663 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
664 "Unexpected number of operands for MRMDestRegFrm");
666 HANDLE_OPERAND(rmRegister)
669 // FIXME: In AVX, the register below becomes the one encoded
670 // in ModRMVEX and the one above the one in the VEX.VVVV field
671 HANDLE_OPERAND(vvvvRegister)
673 HANDLE_OPERAND(roRegister)
674 HANDLE_OPTIONAL(immediate)
676 case X86Local::MRMDestMem:
677 // Operand 1 is a memory operand (possibly SIB-extended)
678 // Operand 2 is a register operand in the Reg/Opcode field.
679 // - In AVX, there is a register operand in the VEX.vvvv field here -
680 // Operand 3 (optional) is an immediate.
682 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
683 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
685 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
686 "Unexpected number of operands for MRMDestMemFrm");
687 HANDLE_OPERAND(memory)
690 // FIXME: In AVX, the register below becomes the one encoded
691 // in ModRMVEX and the one above the one in the VEX.VVVV field
692 HANDLE_OPERAND(vvvvRegister)
694 HANDLE_OPERAND(roRegister)
695 HANDLE_OPTIONAL(immediate)
697 case X86Local::MRMSrcReg:
698 // Operand 1 is a register operand in the Reg/Opcode field.
699 // Operand 2 is a register operand in the R/M field.
700 // - In AVX, there is a register operand in the VEX.vvvv field here -
701 // Operand 3 (optional) is an immediate.
703 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
704 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
705 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
707 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
708 "Unexpected number of operands for MRMSrcRegFrm");
710 HANDLE_OPERAND(roRegister)
713 // FIXME: In AVX, the register below becomes the one encoded
714 // in ModRMVEX and the one above the one in the VEX.VVVV field
715 HANDLE_OPERAND(vvvvRegister)
717 HANDLE_OPERAND(rmRegister)
719 if (HasVEX_4VOp3Prefix)
720 HANDLE_OPERAND(vvvvRegister)
722 HANDLE_OPTIONAL(immediate)
724 case X86Local::MRMSrcMem:
725 // Operand 1 is a register operand in the Reg/Opcode field.
726 // Operand 2 is a memory operand (possibly SIB-extended)
727 // - In AVX, there is a register operand in the VEX.vvvv field here -
728 // Operand 3 (optional) is an immediate.
730 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
731 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
732 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
734 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
735 "Unexpected number of operands for MRMSrcMemFrm");
737 HANDLE_OPERAND(roRegister)
740 // FIXME: In AVX, the register below becomes the one encoded
741 // in ModRMVEX and the one above the one in the VEX.VVVV field
742 HANDLE_OPERAND(vvvvRegister)
744 HANDLE_OPERAND(memory)
746 if (HasVEX_4VOp3Prefix)
747 HANDLE_OPERAND(vvvvRegister)
749 HANDLE_OPTIONAL(immediate)
751 case X86Local::MRM0r:
752 case X86Local::MRM1r:
753 case X86Local::MRM2r:
754 case X86Local::MRM3r:
755 case X86Local::MRM4r:
756 case X86Local::MRM5r:
757 case X86Local::MRM6r:
758 case X86Local::MRM7r:
759 // Operand 1 is a register operand in the R/M field.
760 // Operand 2 (optional) is an immediate or relocation.
762 assert(numPhysicalOperands <= 3 &&
763 "Unexpected number of operands for MRMnRFrm with VEX_4V");
765 assert(numPhysicalOperands <= 2 &&
766 "Unexpected number of operands for MRMnRFrm");
768 HANDLE_OPERAND(vvvvRegister)
769 HANDLE_OPTIONAL(rmRegister)
770 HANDLE_OPTIONAL(relocation)
772 case X86Local::MRM0m:
773 case X86Local::MRM1m:
774 case X86Local::MRM2m:
775 case X86Local::MRM3m:
776 case X86Local::MRM4m:
777 case X86Local::MRM5m:
778 case X86Local::MRM6m:
779 case X86Local::MRM7m:
780 // Operand 1 is a memory operand (possibly SIB-extended)
781 // Operand 2 (optional) is an immediate or relocation.
783 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
784 "Unexpected number of operands for MRMnMFrm");
786 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
787 "Unexpected number of operands for MRMnMFrm");
789 HANDLE_OPERAND(vvvvRegister)
790 HANDLE_OPERAND(memory)
791 HANDLE_OPTIONAL(relocation)
793 case X86Local::RawFrmImm8:
794 // operand 1 is a 16-bit immediate
795 // operand 2 is an 8-bit immediate
796 assert(numPhysicalOperands == 2 &&
797 "Unexpected number of operands for X86Local::RawFrmImm8");
798 HANDLE_OPERAND(immediate)
799 HANDLE_OPERAND(immediate)
801 case X86Local::RawFrmImm16:
802 // operand 1 is a 16-bit immediate
803 // operand 2 is a 16-bit immediate
804 HANDLE_OPERAND(immediate)
805 HANDLE_OPERAND(immediate)
807 case X86Local::MRMInitReg:
812 #undef HANDLE_OPERAND
813 #undef HANDLE_OPTIONAL
816 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
817 // Special cases where the LLVM tables are not complete
819 #define MAP(from, to) \
820 case X86Local::MRM_##from: \
821 filter = new ExactFilter(0x##from); \
824 OpcodeType opcodeType = (OpcodeType)-1;
826 ModRMFilter* filter = NULL;
827 uint8_t opcodeToSet = 0;
830 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
834 opcodeType = TWOBYTE;
838 if (needsModRMForDecode(Form))
839 filter = new ModFilter(isRegFormat(Form));
841 filter = new DumbFilter();
843 #define EXTENSION_TABLE(n) case 0x##n:
844 TWO_BYTE_EXTENSION_TABLES
845 #undef EXTENSION_TABLE
848 llvm_unreachable("Unhandled two-byte extended opcode");
849 case X86Local::MRM0r:
850 case X86Local::MRM1r:
851 case X86Local::MRM2r:
852 case X86Local::MRM3r:
853 case X86Local::MRM4r:
854 case X86Local::MRM5r:
855 case X86Local::MRM6r:
856 case X86Local::MRM7r:
857 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
859 case X86Local::MRM0m:
860 case X86Local::MRM1m:
861 case X86Local::MRM2m:
862 case X86Local::MRM3m:
863 case X86Local::MRM4m:
864 case X86Local::MRM5m:
865 case X86Local::MRM6m:
866 case X86Local::MRM7m:
867 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
873 opcodeToSet = Opcode;
878 opcodeType = THREEBYTE_38;
881 if (needsModRMForDecode(Form))
882 filter = new ModFilter(isRegFormat(Form));
884 filter = new DumbFilter();
886 #define EXTENSION_TABLE(n) case 0x##n:
887 THREE_BYTE_38_EXTENSION_TABLES
888 #undef EXTENSION_TABLE
891 llvm_unreachable("Unhandled two-byte extended opcode");
892 case X86Local::MRM0r:
893 case X86Local::MRM1r:
894 case X86Local::MRM2r:
895 case X86Local::MRM3r:
896 case X86Local::MRM4r:
897 case X86Local::MRM5r:
898 case X86Local::MRM6r:
899 case X86Local::MRM7r:
900 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
902 case X86Local::MRM0m:
903 case X86Local::MRM1m:
904 case X86Local::MRM2m:
905 case X86Local::MRM3m:
906 case X86Local::MRM4m:
907 case X86Local::MRM5m:
908 case X86Local::MRM6m:
909 case X86Local::MRM7m:
910 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
916 opcodeToSet = Opcode;
920 opcodeType = THREEBYTE_3A;
921 if (needsModRMForDecode(Form))
922 filter = new ModFilter(isRegFormat(Form));
924 filter = new DumbFilter();
925 opcodeToSet = Opcode;
928 opcodeType = THREEBYTE_A6;
929 if (needsModRMForDecode(Form))
930 filter = new ModFilter(isRegFormat(Form));
932 filter = new DumbFilter();
933 opcodeToSet = Opcode;
936 opcodeType = THREEBYTE_A7;
937 if (needsModRMForDecode(Form))
938 filter = new ModFilter(isRegFormat(Form));
940 filter = new DumbFilter();
941 opcodeToSet = Opcode;
951 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
952 opcodeType = ONEBYTE;
953 if (Form == X86Local::AddRegFrm) {
954 Spec->modifierType = MODIFIER_MODRM;
955 Spec->modifierBase = Opcode;
956 filter = new AddRegEscapeFilter(Opcode);
958 filter = new EscapeFilter(true, Opcode);
960 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
964 opcodeType = ONEBYTE;
966 #define EXTENSION_TABLE(n) case 0x##n:
967 ONE_BYTE_EXTENSION_TABLES
968 #undef EXTENSION_TABLE
971 llvm_unreachable("Fell through the cracks of a single-byte "
973 case X86Local::MRM0r:
974 case X86Local::MRM1r:
975 case X86Local::MRM2r:
976 case X86Local::MRM3r:
977 case X86Local::MRM4r:
978 case X86Local::MRM5r:
979 case X86Local::MRM6r:
980 case X86Local::MRM7r:
981 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
983 case X86Local::MRM0m:
984 case X86Local::MRM1m:
985 case X86Local::MRM2m:
986 case X86Local::MRM3m:
987 case X86Local::MRM4m:
988 case X86Local::MRM5m:
989 case X86Local::MRM6m:
990 case X86Local::MRM7m:
991 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1004 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1007 if (needsModRMForDecode(Form))
1008 filter = new ModFilter(isRegFormat(Form));
1010 filter = new DumbFilter();
1012 } // switch (Opcode)
1013 opcodeToSet = Opcode;
1014 } // switch (Prefix)
1016 assert(opcodeType != (OpcodeType)-1 &&
1017 "Opcode type not set");
1018 assert(filter && "Filter not set");
1020 if (Form == X86Local::AddRegFrm) {
1021 if(Spec->modifierType != MODIFIER_MODRM) {
1022 assert(opcodeToSet < 0xf9 &&
1023 "Not enough room for all ADDREG_FRM operands");
1025 uint8_t currentOpcode;
1027 for (currentOpcode = opcodeToSet;
1028 currentOpcode < opcodeToSet + 8;
1030 tables.setTableFields(opcodeType,
1034 UID, Is32Bit, IgnoresVEX_L);
1036 Spec->modifierType = MODIFIER_OPCODE;
1037 Spec->modifierBase = opcodeToSet;
1039 // modifierBase was set where MODIFIER_MODRM was set
1040 tables.setTableFields(opcodeType,
1044 UID, Is32Bit, IgnoresVEX_L);
1047 tables.setTableFields(opcodeType,
1051 UID, Is32Bit, IgnoresVEX_L);
1053 Spec->modifierType = MODIFIER_NONE;
1054 Spec->modifierBase = opcodeToSet;
1062 #define TYPE(str, type) if (s == str) return type;
1063 OperandType RecognizableInstr::typeFromString(const std::string &s,
1065 bool hasREX_WPrefix,
1066 bool hasOpSizePrefix) {
1068 // For SSE instructions, we ignore the OpSize prefix and force operand
1070 TYPE("GR16", TYPE_R16)
1071 TYPE("GR32", TYPE_R32)
1072 TYPE("GR64", TYPE_R64)
1074 if(hasREX_WPrefix) {
1075 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1077 TYPE("GR32", TYPE_R32)
1079 if(!hasOpSizePrefix) {
1080 // For instructions without an OpSize prefix, a declared 16-bit register or
1081 // immediate encoding is special.
1082 TYPE("GR16", TYPE_R16)
1083 TYPE("i16imm", TYPE_IMM16)
1085 TYPE("i16mem", TYPE_Mv)
1086 TYPE("i16imm", TYPE_IMMv)
1087 TYPE("i16i8imm", TYPE_IMMv)
1088 TYPE("GR16", TYPE_Rv)
1089 TYPE("i32mem", TYPE_Mv)
1090 TYPE("i32imm", TYPE_IMMv)
1091 TYPE("i32i8imm", TYPE_IMM32)
1092 TYPE("u32u8imm", TYPE_IMM32)
1093 TYPE("GR32", TYPE_Rv)
1094 TYPE("i64mem", TYPE_Mv)
1095 TYPE("i64i32imm", TYPE_IMM64)
1096 TYPE("i64i8imm", TYPE_IMM64)
1097 TYPE("GR64", TYPE_R64)
1098 TYPE("i8mem", TYPE_M8)
1099 TYPE("i8imm", TYPE_IMM8)
1100 TYPE("GR8", TYPE_R8)
1101 TYPE("VR128", TYPE_XMM128)
1102 TYPE("f128mem", TYPE_M128)
1103 TYPE("f256mem", TYPE_M256)
1104 TYPE("FR64", TYPE_XMM64)
1105 TYPE("f64mem", TYPE_M64FP)
1106 TYPE("sdmem", TYPE_M64FP)
1107 TYPE("FR32", TYPE_XMM32)
1108 TYPE("f32mem", TYPE_M32FP)
1109 TYPE("ssmem", TYPE_M32FP)
1110 TYPE("RST", TYPE_ST)
1111 TYPE("i128mem", TYPE_M128)
1112 TYPE("i256mem", TYPE_M256)
1113 TYPE("i64i32imm_pcrel", TYPE_REL64)
1114 TYPE("i16imm_pcrel", TYPE_REL16)
1115 TYPE("i32imm_pcrel", TYPE_REL32)
1116 TYPE("SSECC", TYPE_IMM3)
1117 TYPE("brtarget", TYPE_RELv)
1118 TYPE("uncondbrtarget", TYPE_RELv)
1119 TYPE("brtarget8", TYPE_REL8)
1120 TYPE("f80mem", TYPE_M80FP)
1121 TYPE("lea32mem", TYPE_LEA)
1122 TYPE("lea64_32mem", TYPE_LEA)
1123 TYPE("lea64mem", TYPE_LEA)
1124 TYPE("VR64", TYPE_MM64)
1125 TYPE("i64imm", TYPE_IMMv)
1126 TYPE("opaque32mem", TYPE_M1616)
1127 TYPE("opaque48mem", TYPE_M1632)
1128 TYPE("opaque80mem", TYPE_M1664)
1129 TYPE("opaque512mem", TYPE_M512)
1130 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1131 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1132 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1133 TYPE("offset8", TYPE_MOFFS8)
1134 TYPE("offset16", TYPE_MOFFS16)
1135 TYPE("offset32", TYPE_MOFFS32)
1136 TYPE("offset64", TYPE_MOFFS64)
1137 TYPE("VR256", TYPE_XMM256)
1138 TYPE("GR16_NOAX", TYPE_Rv)
1139 TYPE("GR32_NOAX", TYPE_Rv)
1140 TYPE("GR64_NOAX", TYPE_R64)
1141 errs() << "Unhandled type string " << s << "\n";
1142 llvm_unreachable("Unhandled type string");
1146 #define ENCODING(str, encoding) if (s == str) return encoding;
1147 OperandEncoding RecognizableInstr::immediateEncodingFromString
1148 (const std::string &s,
1149 bool hasOpSizePrefix) {
1150 if(!hasOpSizePrefix) {
1151 // For instructions without an OpSize prefix, a declared 16-bit register or
1152 // immediate encoding is special.
1153 ENCODING("i16imm", ENCODING_IW)
1155 ENCODING("i32i8imm", ENCODING_IB)
1156 ENCODING("u32u8imm", ENCODING_IB)
1157 ENCODING("SSECC", ENCODING_IB)
1158 ENCODING("i16imm", ENCODING_Iv)
1159 ENCODING("i16i8imm", ENCODING_IB)
1160 ENCODING("i32imm", ENCODING_Iv)
1161 ENCODING("i64i32imm", ENCODING_ID)
1162 ENCODING("i64i8imm", ENCODING_IB)
1163 ENCODING("i8imm", ENCODING_IB)
1164 // This is not a typo. Instructions like BLENDVPD put
1165 // register IDs in 8-bit immediates nowadays.
1166 ENCODING("VR256", ENCODING_IB)
1167 ENCODING("VR128", ENCODING_IB)
1168 errs() << "Unhandled immediate encoding " << s << "\n";
1169 llvm_unreachable("Unhandled immediate encoding");
1172 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1173 (const std::string &s,
1174 bool hasOpSizePrefix) {
1175 ENCODING("GR16", ENCODING_RM)
1176 ENCODING("GR32", ENCODING_RM)
1177 ENCODING("GR64", ENCODING_RM)
1178 ENCODING("GR8", ENCODING_RM)
1179 ENCODING("VR128", ENCODING_RM)
1180 ENCODING("FR64", ENCODING_RM)
1181 ENCODING("FR32", ENCODING_RM)
1182 ENCODING("VR64", ENCODING_RM)
1183 ENCODING("VR256", ENCODING_RM)
1184 errs() << "Unhandled R/M register encoding " << s << "\n";
1185 llvm_unreachable("Unhandled R/M register encoding");
1188 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1189 (const std::string &s,
1190 bool hasOpSizePrefix) {
1191 ENCODING("GR16", ENCODING_REG)
1192 ENCODING("GR32", ENCODING_REG)
1193 ENCODING("GR64", ENCODING_REG)
1194 ENCODING("GR8", ENCODING_REG)
1195 ENCODING("VR128", ENCODING_REG)
1196 ENCODING("FR64", ENCODING_REG)
1197 ENCODING("FR32", ENCODING_REG)
1198 ENCODING("VR64", ENCODING_REG)
1199 ENCODING("SEGMENT_REG", ENCODING_REG)
1200 ENCODING("DEBUG_REG", ENCODING_REG)
1201 ENCODING("CONTROL_REG", ENCODING_REG)
1202 ENCODING("VR256", ENCODING_REG)
1203 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1204 llvm_unreachable("Unhandled reg/opcode register encoding");
1207 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1208 (const std::string &s,
1209 bool hasOpSizePrefix) {
1210 ENCODING("GR32", ENCODING_VVVV)
1211 ENCODING("GR64", ENCODING_VVVV)
1212 ENCODING("FR32", ENCODING_VVVV)
1213 ENCODING("FR64", ENCODING_VVVV)
1214 ENCODING("VR128", ENCODING_VVVV)
1215 ENCODING("VR256", ENCODING_VVVV)
1216 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1217 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1220 OperandEncoding RecognizableInstr::memoryEncodingFromString
1221 (const std::string &s,
1222 bool hasOpSizePrefix) {
1223 ENCODING("i16mem", ENCODING_RM)
1224 ENCODING("i32mem", ENCODING_RM)
1225 ENCODING("i64mem", ENCODING_RM)
1226 ENCODING("i8mem", ENCODING_RM)
1227 ENCODING("ssmem", ENCODING_RM)
1228 ENCODING("sdmem", ENCODING_RM)
1229 ENCODING("f128mem", ENCODING_RM)
1230 ENCODING("f256mem", ENCODING_RM)
1231 ENCODING("f64mem", ENCODING_RM)
1232 ENCODING("f32mem", ENCODING_RM)
1233 ENCODING("i128mem", ENCODING_RM)
1234 ENCODING("i256mem", ENCODING_RM)
1235 ENCODING("f80mem", ENCODING_RM)
1236 ENCODING("lea32mem", ENCODING_RM)
1237 ENCODING("lea64_32mem", ENCODING_RM)
1238 ENCODING("lea64mem", ENCODING_RM)
1239 ENCODING("opaque32mem", ENCODING_RM)
1240 ENCODING("opaque48mem", ENCODING_RM)
1241 ENCODING("opaque80mem", ENCODING_RM)
1242 ENCODING("opaque512mem", ENCODING_RM)
1243 errs() << "Unhandled memory encoding " << s << "\n";
1244 llvm_unreachable("Unhandled memory encoding");
1247 OperandEncoding RecognizableInstr::relocationEncodingFromString
1248 (const std::string &s,
1249 bool hasOpSizePrefix) {
1250 if(!hasOpSizePrefix) {
1251 // For instructions without an OpSize prefix, a declared 16-bit register or
1252 // immediate encoding is special.
1253 ENCODING("i16imm", ENCODING_IW)
1255 ENCODING("i16imm", ENCODING_Iv)
1256 ENCODING("i16i8imm", ENCODING_IB)
1257 ENCODING("i32imm", ENCODING_Iv)
1258 ENCODING("i32i8imm", ENCODING_IB)
1259 ENCODING("i64i32imm", ENCODING_ID)
1260 ENCODING("i64i8imm", ENCODING_IB)
1261 ENCODING("i8imm", ENCODING_IB)
1262 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1263 ENCODING("i16imm_pcrel", ENCODING_IW)
1264 ENCODING("i32imm_pcrel", ENCODING_ID)
1265 ENCODING("brtarget", ENCODING_Iv)
1266 ENCODING("brtarget8", ENCODING_IB)
1267 ENCODING("i64imm", ENCODING_IO)
1268 ENCODING("offset8", ENCODING_Ia)
1269 ENCODING("offset16", ENCODING_Ia)
1270 ENCODING("offset32", ENCODING_Ia)
1271 ENCODING("offset64", ENCODING_Ia)
1272 errs() << "Unhandled relocation encoding " << s << "\n";
1273 llvm_unreachable("Unhandled relocation encoding");
1276 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1277 (const std::string &s,
1278 bool hasOpSizePrefix) {
1279 ENCODING("RST", ENCODING_I)
1280 ENCODING("GR32", ENCODING_Rv)
1281 ENCODING("GR64", ENCODING_RO)
1282 ENCODING("GR16", ENCODING_Rv)
1283 ENCODING("GR8", ENCODING_RB)
1284 ENCODING("GR16_NOAX", ENCODING_Rv)
1285 ENCODING("GR32_NOAX", ENCODING_Rv)
1286 ENCODING("GR64_NOAX", ENCODING_RO)
1287 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1288 llvm_unreachable("Unhandled opcode modifier encoding");