1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
39 // A clone of X86 since we can't depend on something that is generated.
49 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
50 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
51 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
52 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55 #define MAP(from, to) MRM_##from = to,
64 D8 = 3, D9 = 4, DA = 5, DB = 6,
65 DC = 7, DD = 8, DE = 9, DF = 10,
68 P_0F_AE = 16, P_0F_01 = 17
72 // If rows are added to the opcode extension tables, then corresponding entries
73 // must be added here.
75 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
76 // that byte to ONE_BYTE_EXTENSION_TABLES.
78 // If the row corresponds to two bytes where the first is 0f, add an entry for
79 // the second byte to TWO_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to some other set of bytes, you will need to modify
82 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
83 // to the X86 TD files, except in two cases: if the first two bytes of such a
84 // new combination are 0f 38 or 0f 3a, you just have to add maps called
85 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
86 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
87 // in RecognizableInstr::emitDecodePath().
89 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(d1) \
101 EXTENSION_TABLE(d2) \
102 EXTENSION_TABLE(d3) \
103 EXTENSION_TABLE(f6) \
104 EXTENSION_TABLE(f7) \
105 EXTENSION_TABLE(fe) \
108 #define TWO_BYTE_EXTENSION_TABLES \
109 EXTENSION_TABLE(00) \
110 EXTENSION_TABLE(01) \
111 EXTENSION_TABLE(18) \
112 EXTENSION_TABLE(71) \
113 EXTENSION_TABLE(72) \
114 EXTENSION_TABLE(73) \
115 EXTENSION_TABLE(ae) \
116 EXTENSION_TABLE(b9) \
117 EXTENSION_TABLE(ba) \
120 using namespace X86Disassembler;
122 /// needsModRMForDecode - Indicates whether a particular instruction requires a
123 /// ModR/M byte for the instruction to be properly decoded. For example, a
124 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
127 /// @param form - The form of the instruction.
128 /// @return - true if the form implies that a ModR/M byte is required, false
130 static bool needsModRMForDecode(uint8_t form) {
131 if (form == X86Local::MRMDestReg ||
132 form == X86Local::MRMDestMem ||
133 form == X86Local::MRMSrcReg ||
134 form == X86Local::MRMSrcMem ||
135 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
136 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
142 /// isRegFormat - Indicates whether a particular form requires the Mod field of
143 /// the ModR/M byte to be 0b11.
145 /// @param form - The form of the instruction.
146 /// @return - true if the form implies that Mod must be 0b11, false
148 static bool isRegFormat(uint8_t form) {
149 if (form == X86Local::MRMDestReg ||
150 form == X86Local::MRMSrcReg ||
151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
157 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
158 /// Useful for switch statements and the like.
160 /// @param init - A reference to the BitsInit to be decoded.
161 /// @return - The field, with the first bit in the BitsInit as the lowest
163 static uint8_t byteFromBitsInit(BitsInit &init) {
164 int width = init.getNumBits();
166 assert(width <= 8 && "Field is too large for uint8_t!");
173 for (index = 0; index < width; index++) {
174 if (static_cast<BitInit*>(init.getBit(index))->getValue())
183 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
184 /// name of the field.
186 /// @param rec - The record from which to extract the value.
187 /// @param name - The name of the field in the record.
188 /// @return - The field, as translated by byteFromBitsInit().
189 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
190 BitsInit* bits = rec->getValueAsBitsInit(name);
191 return byteFromBitsInit(*bits);
194 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
195 const CodeGenInstruction &insn,
200 Name = Rec->getName();
201 Spec = &tables.specForUID(UID);
203 if (!Rec->isSubClassOf("X86Inst")) {
204 ShouldBeEmitted = false;
208 Prefix = byteFromRec(Rec, "Prefix");
209 Opcode = byteFromRec(Rec, "Opcode");
210 Form = byteFromRec(Rec, "FormBits");
211 SegOvr = byteFromRec(Rec, "SegOvrBits");
213 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
214 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
215 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
216 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
218 Name = Rec->getName();
219 AsmString = Rec->getValueAsString("AsmString");
221 Operands = &insn.OperandList;
223 IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos);
224 HasFROperands = false;
226 ShouldBeEmitted = true;
229 void RecognizableInstr::processInstr(DisassemblerTables &tables,
230 const CodeGenInstruction &insn,
233 // Ignore "asm parser only" instructions.
234 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
237 RecognizableInstr recogInstr(tables, insn, uid);
239 recogInstr.emitInstructionSpecifier(tables);
241 if (recogInstr.shouldBeEmitted())
242 recogInstr.emitDecodePath(tables);
245 InstructionContext RecognizableInstr::insnContext() const {
246 InstructionContext insnContext;
248 if (Name.find("64") != Name.npos || HasREX_WPrefix) {
249 if (HasREX_WPrefix && HasOpSizePrefix)
250 insnContext = IC_64BIT_REXW_OPSIZE;
251 else if (HasOpSizePrefix)
252 insnContext = IC_64BIT_OPSIZE;
253 else if (HasREX_WPrefix && Prefix == X86Local::XS)
254 insnContext = IC_64BIT_REXW_XS;
255 else if (HasREX_WPrefix && Prefix == X86Local::XD)
256 insnContext = IC_64BIT_REXW_XD;
257 else if (Prefix == X86Local::XD)
258 insnContext = IC_64BIT_XD;
259 else if (Prefix == X86Local::XS)
260 insnContext = IC_64BIT_XS;
261 else if (HasREX_WPrefix)
262 insnContext = IC_64BIT_REXW;
264 insnContext = IC_64BIT;
267 insnContext = IC_OPSIZE;
268 else if (Prefix == X86Local::XD)
270 else if (Prefix == X86Local::XS)
279 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
280 // Filter out intrinsics
282 if (!Rec->isSubClassOf("X86Inst"))
283 return FILTER_STRONG;
285 if (Form == X86Local::Pseudo ||
287 return FILTER_STRONG;
289 if (Form == X86Local::MRMInitReg)
290 return FILTER_STRONG;
293 // Filter out instructions with a LOCK prefix;
294 // prefer forms that do not have the prefix
298 // Filter out artificial instructions
300 if (Name.find("TAILJMP") != Name.npos ||
301 Name.find("_Int") != Name.npos ||
302 Name.find("_int") != Name.npos ||
303 Name.find("Int_") != Name.npos ||
304 Name.find("_NOREX") != Name.npos ||
305 Name.find("_TC") != Name.npos ||
306 Name.find("EH_RETURN") != Name.npos ||
307 Name.find("V_SET") != Name.npos ||
308 Name.find("LOCK_") != Name.npos ||
309 Name.find("WIN") != Name.npos)
310 return FILTER_STRONG;
314 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
316 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
319 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
321 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
323 if (Name.find("Fs") != Name.npos)
325 if (Name == "MOVLPDrr" ||
326 Name == "MOVLPSrr" ||
332 Name == "MOVSX16rm8" ||
333 Name == "MOVSX16rr8" ||
334 Name == "MOVZX16rm8" ||
335 Name == "MOVZX16rr8" ||
336 Name == "PUSH32i16" ||
337 Name == "PUSH64i16" ||
338 Name == "MOVPQI2QImr" ||
343 Name == "MMX_MOVD64rrv164" ||
344 Name == "CRC32m16" ||
345 Name == "MOV64ri64i32" ||
349 // Filter out instructions with segment override prefixes.
350 // They're too messy to handle now and we'll special case them if needed.
353 return FILTER_STRONG;
355 // Filter out instructions that can't be printed.
357 if (AsmString.size() == 0)
358 return FILTER_STRONG;
360 // Filter out instructions with subreg operands.
362 if (AsmString.find("subreg") != AsmString.npos)
363 return FILTER_STRONG;
365 if (HasFROperands && Name.find("MOV") != Name.npos &&
366 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
367 (Name.find("to") != Name.npos)))
370 return FILTER_NORMAL;
373 void RecognizableInstr::handleOperand(
375 unsigned &operandIndex,
376 unsigned &physicalOperandIndex,
377 unsigned &numPhysicalOperands,
378 unsigned *operandMapping,
379 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
381 if (physicalOperandIndex >= numPhysicalOperands)
384 assert(physicalOperandIndex < numPhysicalOperands);
387 while (operandMapping[operandIndex] != operandIndex) {
388 Spec->operands[operandIndex].encoding = ENCODING_DUP;
389 Spec->operands[operandIndex].type =
390 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
394 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
396 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
398 Spec->operands[operandIndex].type = typeFromString(typeName,
404 ++physicalOperandIndex;
407 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
410 if (!Rec->isSubClassOf("X86Inst"))
415 Spec->filtered = true;
418 ShouldBeEmitted = false;
424 Spec->insnContext = insnContext();
426 const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
428 unsigned operandIndex;
429 unsigned numOperands = OperandList.size();
430 unsigned numPhysicalOperands = 0;
432 // operandMapping maps from operands in OperandList to their originals.
433 // If operandMapping[i] != i, then the entry is a duplicate.
434 unsigned operandMapping[X86_MAX_OPERANDS];
436 bool hasFROperands = false;
438 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
440 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
441 if (OperandList[operandIndex].Constraints.size()) {
442 const CodeGenInstruction::ConstraintInfo &Constraint =
443 OperandList[operandIndex].Constraints[0];
444 if (Constraint.isTied()) {
445 operandMapping[operandIndex] = Constraint.getTiedOperand();
447 ++numPhysicalOperands;
448 operandMapping[operandIndex] = operandIndex;
451 ++numPhysicalOperands;
452 operandMapping[operandIndex] = operandIndex;
455 const std::string &recName = OperandList[operandIndex].Rec->getName();
457 if (recName.find("FR") != recName.npos)
458 hasFROperands = true;
461 if (hasFROperands && Name.find("MOV") != Name.npos &&
462 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
463 (Name.find("to") != Name.npos)))
464 ShouldBeEmitted = false;
466 if (!ShouldBeEmitted)
469 #define HANDLE_OPERAND(class) \
470 handleOperand(false, \
472 physicalOperandIndex, \
473 numPhysicalOperands, \
475 class##EncodingFromString);
477 #define HANDLE_OPTIONAL(class) \
478 handleOperand(true, \
480 physicalOperandIndex, \
481 numPhysicalOperands, \
483 class##EncodingFromString);
485 // operandIndex should always be < numOperands
487 // physicalOperandIndex should always be < numPhysicalOperands
488 unsigned physicalOperandIndex = 0;
491 case X86Local::RawFrm:
492 // Operand 1 (optional) is an address or immediate.
493 // Operand 2 (optional) is an immediate.
494 assert(numPhysicalOperands <= 2 &&
495 "Unexpected number of operands for RawFrm");
496 HANDLE_OPTIONAL(relocation)
497 HANDLE_OPTIONAL(immediate)
499 case X86Local::AddRegFrm:
500 // Operand 1 is added to the opcode.
501 // Operand 2 (optional) is an address.
502 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
503 "Unexpected number of operands for AddRegFrm");
504 HANDLE_OPERAND(opcodeModifier)
505 HANDLE_OPTIONAL(relocation)
507 case X86Local::MRMDestReg:
508 // Operand 1 is a register operand in the R/M field.
509 // Operand 2 is a register operand in the Reg/Opcode field.
510 // Operand 3 (optional) is an immediate.
511 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
512 "Unexpected number of operands for MRMDestRegFrm");
513 HANDLE_OPERAND(rmRegister)
514 HANDLE_OPERAND(roRegister)
515 HANDLE_OPTIONAL(immediate)
517 case X86Local::MRMDestMem:
518 // Operand 1 is a memory operand (possibly SIB-extended)
519 // Operand 2 is a register operand in the Reg/Opcode field.
520 // Operand 3 (optional) is an immediate.
521 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
522 "Unexpected number of operands for MRMDestMemFrm");
523 HANDLE_OPERAND(memory)
524 HANDLE_OPERAND(roRegister)
525 HANDLE_OPTIONAL(immediate)
527 case X86Local::MRMSrcReg:
528 // Operand 1 is a register operand in the Reg/Opcode field.
529 // Operand 2 is a register operand in the R/M field.
530 // Operand 3 (optional) is an immediate.
531 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
532 "Unexpected number of operands for MRMSrcRegFrm");
533 HANDLE_OPERAND(roRegister)
534 HANDLE_OPERAND(rmRegister)
535 HANDLE_OPTIONAL(immediate)
537 case X86Local::MRMSrcMem:
538 // Operand 1 is a register operand in the Reg/Opcode field.
539 // Operand 2 is a memory operand (possibly SIB-extended)
540 // Operand 3 (optional) is an immediate.
541 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
542 "Unexpected number of operands for MRMSrcMemFrm");
543 HANDLE_OPERAND(roRegister)
544 HANDLE_OPERAND(memory)
545 HANDLE_OPTIONAL(immediate)
547 case X86Local::MRM0r:
548 case X86Local::MRM1r:
549 case X86Local::MRM2r:
550 case X86Local::MRM3r:
551 case X86Local::MRM4r:
552 case X86Local::MRM5r:
553 case X86Local::MRM6r:
554 case X86Local::MRM7r:
555 // Operand 1 is a register operand in the R/M field.
556 // Operand 2 (optional) is an immediate or relocation.
557 assert(numPhysicalOperands <= 2 &&
558 "Unexpected number of operands for MRMnRFrm");
559 HANDLE_OPTIONAL(rmRegister)
560 HANDLE_OPTIONAL(relocation)
562 case X86Local::MRM0m:
563 case X86Local::MRM1m:
564 case X86Local::MRM2m:
565 case X86Local::MRM3m:
566 case X86Local::MRM4m:
567 case X86Local::MRM5m:
568 case X86Local::MRM6m:
569 case X86Local::MRM7m:
570 // Operand 1 is a memory operand (possibly SIB-extended)
571 // Operand 2 (optional) is an immediate or relocation.
572 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
573 "Unexpected number of operands for MRMnMFrm");
574 HANDLE_OPERAND(memory)
575 HANDLE_OPTIONAL(relocation)
577 case X86Local::MRMInitReg:
582 #undef HANDLE_OPERAND
583 #undef HANDLE_OPTIONAL
586 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
587 // Special cases where the LLVM tables are not complete
589 #define MAP(from, to) \
590 case X86Local::MRM_##from: \
591 filter = new ExactFilter(0x##from); \
594 OpcodeType opcodeType = (OpcodeType)-1;
596 ModRMFilter* filter = NULL;
597 uint8_t opcodeToSet = 0;
600 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
604 opcodeType = TWOBYTE;
608 if (needsModRMForDecode(Form))
609 filter = new ModFilter(isRegFormat(Form));
611 filter = new DumbFilter();
613 #define EXTENSION_TABLE(n) case 0x##n:
614 TWO_BYTE_EXTENSION_TABLES
615 #undef EXTENSION_TABLE
618 llvm_unreachable("Unhandled two-byte extended opcode");
619 case X86Local::MRM0r:
620 case X86Local::MRM1r:
621 case X86Local::MRM2r:
622 case X86Local::MRM3r:
623 case X86Local::MRM4r:
624 case X86Local::MRM5r:
625 case X86Local::MRM6r:
626 case X86Local::MRM7r:
627 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
629 case X86Local::MRM0m:
630 case X86Local::MRM1m:
631 case X86Local::MRM2m:
632 case X86Local::MRM3m:
633 case X86Local::MRM4m:
634 case X86Local::MRM5m:
635 case X86Local::MRM6m:
636 case X86Local::MRM7m:
637 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
643 opcodeToSet = Opcode;
646 opcodeType = THREEBYTE_38;
647 if (needsModRMForDecode(Form))
648 filter = new ModFilter(isRegFormat(Form));
650 filter = new DumbFilter();
651 opcodeToSet = Opcode;
654 opcodeType = THREEBYTE_3A;
655 if (needsModRMForDecode(Form))
656 filter = new ModFilter(isRegFormat(Form));
658 filter = new DumbFilter();
659 opcodeToSet = Opcode;
669 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
670 opcodeType = ONEBYTE;
671 if (Form == X86Local::AddRegFrm) {
672 Spec->modifierType = MODIFIER_MODRM;
673 Spec->modifierBase = Opcode;
674 filter = new AddRegEscapeFilter(Opcode);
676 filter = new EscapeFilter(true, Opcode);
678 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
681 opcodeType = ONEBYTE;
683 #define EXTENSION_TABLE(n) case 0x##n:
684 ONE_BYTE_EXTENSION_TABLES
685 #undef EXTENSION_TABLE
688 llvm_unreachable("Fell through the cracks of a single-byte "
690 case X86Local::MRM0r:
691 case X86Local::MRM1r:
692 case X86Local::MRM2r:
693 case X86Local::MRM3r:
694 case X86Local::MRM4r:
695 case X86Local::MRM5r:
696 case X86Local::MRM6r:
697 case X86Local::MRM7r:
698 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
700 case X86Local::MRM0m:
701 case X86Local::MRM1m:
702 case X86Local::MRM2m:
703 case X86Local::MRM3m:
704 case X86Local::MRM4m:
705 case X86Local::MRM5m:
706 case X86Local::MRM6m:
707 case X86Local::MRM7m:
708 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
721 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
724 if (needsModRMForDecode(Form))
725 filter = new ModFilter(isRegFormat(Form));
727 filter = new DumbFilter();
730 opcodeToSet = Opcode;
733 assert(opcodeType != (OpcodeType)-1 &&
734 "Opcode type not set");
735 assert(filter && "Filter not set");
737 if (Form == X86Local::AddRegFrm) {
738 if(Spec->modifierType != MODIFIER_MODRM) {
739 assert(opcodeToSet < 0xf9 &&
740 "Not enough room for all ADDREG_FRM operands");
742 uint8_t currentOpcode;
744 for (currentOpcode = opcodeToSet;
745 currentOpcode < opcodeToSet + 8;
747 tables.setTableFields(opcodeType,
753 Spec->modifierType = MODIFIER_OPCODE;
754 Spec->modifierBase = opcodeToSet;
756 // modifierBase was set where MODIFIER_MODRM was set
757 tables.setTableFields(opcodeType,
764 tables.setTableFields(opcodeType,
770 Spec->modifierType = MODIFIER_NONE;
771 Spec->modifierBase = opcodeToSet;
779 #define TYPE(str, type) if (s == str) return type;
780 OperandType RecognizableInstr::typeFromString(const std::string &s,
783 bool hasOpSizePrefix) {
785 // For SSE instructions, we ignore the OpSize prefix and force operand
787 TYPE("GR16", TYPE_R16)
788 TYPE("GR32", TYPE_R32)
789 TYPE("GR64", TYPE_R64)
792 // For instructions with a REX_W prefix, a declared 32-bit register encoding
794 TYPE("GR32", TYPE_R32)
796 if(!hasOpSizePrefix) {
797 // For instructions without an OpSize prefix, a declared 16-bit register or
798 // immediate encoding is special.
799 TYPE("GR16", TYPE_R16)
800 TYPE("i16imm", TYPE_IMM16)
802 TYPE("i16mem", TYPE_Mv)
803 TYPE("i16imm", TYPE_IMMv)
804 TYPE("i16i8imm", TYPE_IMMv)
805 TYPE("GR16", TYPE_Rv)
806 TYPE("i32mem", TYPE_Mv)
807 TYPE("i32imm", TYPE_IMMv)
808 TYPE("i32i8imm", TYPE_IMM32)
809 TYPE("GR32", TYPE_Rv)
810 TYPE("i64mem", TYPE_Mv)
811 TYPE("i64i32imm", TYPE_IMM64)
812 TYPE("i64i8imm", TYPE_IMM64)
813 TYPE("GR64", TYPE_R64)
814 TYPE("i8mem", TYPE_M8)
815 TYPE("i8imm", TYPE_IMM8)
817 TYPE("VR128", TYPE_XMM128)
818 TYPE("f128mem", TYPE_M128)
819 TYPE("FR64", TYPE_XMM64)
820 TYPE("f64mem", TYPE_M64FP)
821 TYPE("FR32", TYPE_XMM32)
822 TYPE("f32mem", TYPE_M32FP)
824 TYPE("i128mem", TYPE_M128)
825 TYPE("i64i32imm_pcrel", TYPE_REL64)
826 TYPE("i32imm_pcrel", TYPE_REL32)
827 TYPE("SSECC", TYPE_IMM3)
828 TYPE("brtarget", TYPE_RELv)
829 TYPE("brtarget8", TYPE_REL8)
830 TYPE("f80mem", TYPE_M80FP)
831 TYPE("lea32mem", TYPE_LEA)
832 TYPE("lea64_32mem", TYPE_LEA)
833 TYPE("lea64mem", TYPE_LEA)
834 TYPE("VR64", TYPE_MM64)
835 TYPE("i64imm", TYPE_IMMv)
836 TYPE("opaque32mem", TYPE_M1616)
837 TYPE("opaque48mem", TYPE_M1632)
838 TYPE("opaque80mem", TYPE_M1664)
839 TYPE("opaque512mem", TYPE_M512)
840 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
841 TYPE("DEBUG_REG", TYPE_DEBUGREG)
842 TYPE("CONTROL_REG", TYPE_CONTROLREG)
843 TYPE("offset8", TYPE_MOFFS8)
844 TYPE("offset16", TYPE_MOFFS16)
845 TYPE("offset32", TYPE_MOFFS32)
846 TYPE("offset64", TYPE_MOFFS64)
847 errs() << "Unhandled type string " << s << "\n";
848 llvm_unreachable("Unhandled type string");
852 #define ENCODING(str, encoding) if (s == str) return encoding;
853 OperandEncoding RecognizableInstr::immediateEncodingFromString
854 (const std::string &s,
855 bool hasOpSizePrefix) {
856 if(!hasOpSizePrefix) {
857 // For instructions without an OpSize prefix, a declared 16-bit register or
858 // immediate encoding is special.
859 ENCODING("i16imm", ENCODING_IW)
861 ENCODING("i32i8imm", ENCODING_IB)
862 ENCODING("SSECC", ENCODING_IB)
863 ENCODING("i16imm", ENCODING_Iv)
864 ENCODING("i16i8imm", ENCODING_IB)
865 ENCODING("i32imm", ENCODING_Iv)
866 ENCODING("i64i32imm", ENCODING_ID)
867 ENCODING("i64i8imm", ENCODING_IB)
868 ENCODING("i8imm", ENCODING_IB)
869 errs() << "Unhandled immediate encoding " << s << "\n";
870 llvm_unreachable("Unhandled immediate encoding");
873 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
874 (const std::string &s,
875 bool hasOpSizePrefix) {
876 ENCODING("GR16", ENCODING_RM)
877 ENCODING("GR32", ENCODING_RM)
878 ENCODING("GR64", ENCODING_RM)
879 ENCODING("GR8", ENCODING_RM)
880 ENCODING("VR128", ENCODING_RM)
881 ENCODING("FR64", ENCODING_RM)
882 ENCODING("FR32", ENCODING_RM)
883 ENCODING("VR64", ENCODING_RM)
884 errs() << "Unhandled R/M register encoding " << s << "\n";
885 llvm_unreachable("Unhandled R/M register encoding");
888 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
889 (const std::string &s,
890 bool hasOpSizePrefix) {
891 ENCODING("GR16", ENCODING_REG)
892 ENCODING("GR32", ENCODING_REG)
893 ENCODING("GR64", ENCODING_REG)
894 ENCODING("GR8", ENCODING_REG)
895 ENCODING("VR128", ENCODING_REG)
896 ENCODING("FR64", ENCODING_REG)
897 ENCODING("FR32", ENCODING_REG)
898 ENCODING("VR64", ENCODING_REG)
899 ENCODING("SEGMENT_REG", ENCODING_REG)
900 ENCODING("DEBUG_REG", ENCODING_REG)
901 ENCODING("CONTROL_REG", ENCODING_REG)
902 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
903 llvm_unreachable("Unhandled reg/opcode register encoding");
906 OperandEncoding RecognizableInstr::memoryEncodingFromString
907 (const std::string &s,
908 bool hasOpSizePrefix) {
909 ENCODING("i16mem", ENCODING_RM)
910 ENCODING("i32mem", ENCODING_RM)
911 ENCODING("i64mem", ENCODING_RM)
912 ENCODING("i8mem", ENCODING_RM)
913 ENCODING("f128mem", ENCODING_RM)
914 ENCODING("f64mem", ENCODING_RM)
915 ENCODING("f32mem", ENCODING_RM)
916 ENCODING("i128mem", ENCODING_RM)
917 ENCODING("f80mem", ENCODING_RM)
918 ENCODING("lea32mem", ENCODING_RM)
919 ENCODING("lea64_32mem", ENCODING_RM)
920 ENCODING("lea64mem", ENCODING_RM)
921 ENCODING("opaque32mem", ENCODING_RM)
922 ENCODING("opaque48mem", ENCODING_RM)
923 ENCODING("opaque80mem", ENCODING_RM)
924 ENCODING("opaque512mem", ENCODING_RM)
925 errs() << "Unhandled memory encoding " << s << "\n";
926 llvm_unreachable("Unhandled memory encoding");
929 OperandEncoding RecognizableInstr::relocationEncodingFromString
930 (const std::string &s,
931 bool hasOpSizePrefix) {
932 if(!hasOpSizePrefix) {
933 // For instructions without an OpSize prefix, a declared 16-bit register or
934 // immediate encoding is special.
935 ENCODING("i16imm", ENCODING_IW)
937 ENCODING("i16imm", ENCODING_Iv)
938 ENCODING("i16i8imm", ENCODING_IB)
939 ENCODING("i32imm", ENCODING_Iv)
940 ENCODING("i32i8imm", ENCODING_IB)
941 ENCODING("i64i32imm", ENCODING_ID)
942 ENCODING("i64i8imm", ENCODING_IB)
943 ENCODING("i8imm", ENCODING_IB)
944 ENCODING("i64i32imm_pcrel", ENCODING_ID)
945 ENCODING("i32imm_pcrel", ENCODING_ID)
946 ENCODING("brtarget", ENCODING_Iv)
947 ENCODING("brtarget8", ENCODING_IB)
948 ENCODING("i64imm", ENCODING_IO)
949 ENCODING("offset8", ENCODING_Ia)
950 ENCODING("offset16", ENCODING_Ia)
951 ENCODING("offset32", ENCODING_Ia)
952 ENCODING("offset64", ENCODING_Ia)
953 errs() << "Unhandled relocation encoding " << s << "\n";
954 llvm_unreachable("Unhandled relocation encoding");
957 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
958 (const std::string &s,
959 bool hasOpSizePrefix) {
960 ENCODING("RST", ENCODING_I)
961 ENCODING("GR32", ENCODING_Rv)
962 ENCODING("GR64", ENCODING_RO)
963 ENCODING("GR16", ENCODING_Rv)
964 ENCODING("GR8", ENCODING_RB)
965 errs() << "Unhandled opcode modifier encoding " << s << "\n";
966 llvm_unreachable("Unhandled opcode modifier encoding");