1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
66 MRMXr = 14, MRMXm = 15,
67 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
68 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
69 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
70 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
73 #define MAP(from, to) MRM_##from = to,
80 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6,
81 D8 = 7, D9 = 8, DA = 9, DB = 10,
82 DC = 11, DD = 12, DE = 13, DF = 14,
87 PS = 1, PD = 2, XS = 3, XD = 4
91 VEX = 1, XOP = 2, EVEX = 3
95 OpSize16 = 1, OpSize32 = 2
99 using namespace X86Disassembler;
101 /// isRegFormat - Indicates whether a particular form requires the Mod field of
102 /// the ModR/M byte to be 0b11.
104 /// @param form - The form of the instruction.
105 /// @return - true if the form implies that Mod must be 0b11, false
107 static bool isRegFormat(uint8_t form) {
108 return (form == X86Local::MRMDestReg ||
109 form == X86Local::MRMSrcReg ||
110 form == X86Local::MRMXr ||
111 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
114 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
115 /// Useful for switch statements and the like.
117 /// @param init - A reference to the BitsInit to be decoded.
118 /// @return - The field, with the first bit in the BitsInit as the lowest
120 static uint8_t byteFromBitsInit(BitsInit &init) {
121 int width = init.getNumBits();
123 assert(width <= 8 && "Field is too large for uint8_t!");
130 for (index = 0; index < width; index++) {
131 if (static_cast<BitInit*>(init.getBit(index))->getValue())
140 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
141 /// name of the field.
143 /// @param rec - The record from which to extract the value.
144 /// @param name - The name of the field in the record.
145 /// @return - The field, as translated by byteFromBitsInit().
146 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
147 BitsInit* bits = rec->getValueAsBitsInit(name);
148 return byteFromBitsInit(*bits);
151 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
152 const CodeGenInstruction &insn,
157 Name = Rec->getName();
158 Spec = &tables.specForUID(UID);
160 if (!Rec->isSubClassOf("X86Inst")) {
161 ShouldBeEmitted = false;
165 OpPrefix = byteFromRec(Rec->getValueAsDef("OpPrefix"), "Value");
166 OpMap = byteFromRec(Rec->getValueAsDef("OpMap"), "Value");
167 Opcode = byteFromRec(Rec, "Opcode");
168 Form = byteFromRec(Rec, "FormBits");
169 Encoding = byteFromRec(Rec->getValueAsDef("OpEnc"), "Value");
171 OpSize = byteFromRec(Rec->getValueAsDef("OpSize"), "Value");
172 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
173 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
174 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
175 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
176 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
177 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
178 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
179 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
180 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
181 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
182 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
183 HasREPPrefix = Rec->getValueAsBit("hasREPPrefix");
184 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
185 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
187 Name = Rec->getName();
188 AsmString = Rec->getValueAsString("AsmString");
190 Operands = &insn.Operands.OperandList;
192 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
194 // Check for 64-bit inst which does not require REX
197 // FIXME: Is there some better way to check for In64BitMode?
198 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
199 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
200 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
201 Predicates[i]->getName().find("In32Bit") != Name.npos) {
205 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
211 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
212 ShouldBeEmitted = false;
216 // Special case since there is no attribute class for 64-bit and VEX
217 if (Name == "VMASKMOVDQU64") {
218 ShouldBeEmitted = false;
222 ShouldBeEmitted = true;
225 void RecognizableInstr::processInstr(DisassemblerTables &tables,
226 const CodeGenInstruction &insn,
229 // Ignore "asm parser only" instructions.
230 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
233 RecognizableInstr recogInstr(tables, insn, uid);
235 if (recogInstr.shouldBeEmitted()) {
236 recogInstr.emitInstructionSpecifier();
237 recogInstr.emitDecodePath(tables);
241 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
242 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
243 (HasEVEX_KZ ? n##_KZ : \
244 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
246 InstructionContext RecognizableInstr::insnContext() const {
247 InstructionContext insnContext;
249 if (Encoding == X86Local::EVEX) {
250 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
251 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
252 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
255 if (HasVEX_LPrefix && HasVEX_WPrefix) {
256 if (OpPrefix == X86Local::PD)
257 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
258 else if (OpPrefix == X86Local::XS)
259 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
260 else if (OpPrefix == X86Local::XD)
261 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
262 else if (OpPrefix == X86Local::PS)
263 insnContext = EVEX_KB(IC_EVEX_L_W);
265 errs() << "Instruction does not use a prefix: " << Name << "\n";
266 llvm_unreachable("Invalid prefix");
268 } else if (HasVEX_LPrefix) {
270 if (OpPrefix == X86Local::PD)
271 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
272 else if (OpPrefix == X86Local::XS)
273 insnContext = EVEX_KB(IC_EVEX_L_XS);
274 else if (OpPrefix == X86Local::XD)
275 insnContext = EVEX_KB(IC_EVEX_L_XD);
276 else if (OpPrefix == X86Local::PS)
277 insnContext = EVEX_KB(IC_EVEX_L);
279 errs() << "Instruction does not use a prefix: " << Name << "\n";
280 llvm_unreachable("Invalid prefix");
283 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
285 if (OpPrefix == X86Local::PD)
286 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
287 else if (OpPrefix == X86Local::XS)
288 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
289 else if (OpPrefix == X86Local::XD)
290 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
291 else if (OpPrefix == X86Local::PS)
292 insnContext = EVEX_KB(IC_EVEX_L2_W);
294 errs() << "Instruction does not use a prefix: " << Name << "\n";
295 llvm_unreachable("Invalid prefix");
297 } else if (HasEVEX_L2Prefix) {
299 if (OpPrefix == X86Local::PD)
300 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
301 else if (OpPrefix == X86Local::XD)
302 insnContext = EVEX_KB(IC_EVEX_L2_XD);
303 else if (OpPrefix == X86Local::XS)
304 insnContext = EVEX_KB(IC_EVEX_L2_XS);
305 else if (OpPrefix == X86Local::PS)
306 insnContext = EVEX_KB(IC_EVEX_L2);
308 errs() << "Instruction does not use a prefix: " << Name << "\n";
309 llvm_unreachable("Invalid prefix");
312 else if (HasVEX_WPrefix) {
314 if (OpPrefix == X86Local::PD)
315 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
316 else if (OpPrefix == X86Local::XS)
317 insnContext = EVEX_KB(IC_EVEX_W_XS);
318 else if (OpPrefix == X86Local::XD)
319 insnContext = EVEX_KB(IC_EVEX_W_XD);
320 else if (OpPrefix == X86Local::PS)
321 insnContext = EVEX_KB(IC_EVEX_W);
323 errs() << "Instruction does not use a prefix: " << Name << "\n";
324 llvm_unreachable("Invalid prefix");
328 else if (OpPrefix == X86Local::PD)
329 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
330 else if (OpPrefix == X86Local::XD)
331 insnContext = EVEX_KB(IC_EVEX_XD);
332 else if (OpPrefix == X86Local::XS)
333 insnContext = EVEX_KB(IC_EVEX_XS);
335 insnContext = EVEX_KB(IC_EVEX);
337 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
338 if (HasVEX_LPrefix && HasVEX_WPrefix) {
339 if (OpPrefix == X86Local::PD)
340 insnContext = IC_VEX_L_W_OPSIZE;
341 else if (OpPrefix == X86Local::XS)
342 insnContext = IC_VEX_L_W_XS;
343 else if (OpPrefix == X86Local::XD)
344 insnContext = IC_VEX_L_W_XD;
345 else if (OpPrefix == X86Local::PS)
346 insnContext = IC_VEX_L_W;
348 errs() << "Instruction does not use a prefix: " << Name << "\n";
349 llvm_unreachable("Invalid prefix");
351 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
352 insnContext = IC_VEX_L_OPSIZE;
353 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
354 insnContext = IC_VEX_W_OPSIZE;
355 else if (OpPrefix == X86Local::PD)
356 insnContext = IC_VEX_OPSIZE;
357 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
358 insnContext = IC_VEX_L_XS;
359 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
360 insnContext = IC_VEX_L_XD;
361 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
362 insnContext = IC_VEX_W_XS;
363 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
364 insnContext = IC_VEX_W_XD;
365 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS)
366 insnContext = IC_VEX_W;
367 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
368 insnContext = IC_VEX_L;
369 else if (OpPrefix == X86Local::XD)
370 insnContext = IC_VEX_XD;
371 else if (OpPrefix == X86Local::XS)
372 insnContext = IC_VEX_XS;
373 else if (OpPrefix == X86Local::PS)
374 insnContext = IC_VEX;
376 errs() << "Instruction does not use a prefix: " << Name << "\n";
377 llvm_unreachable("Invalid prefix");
379 } else if (Is64Bit || HasREX_WPrefix) {
380 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
381 insnContext = IC_64BIT_REXW_OPSIZE;
382 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
383 insnContext = IC_64BIT_XD_OPSIZE;
384 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
385 insnContext = IC_64BIT_XS_OPSIZE;
386 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
387 insnContext = IC_64BIT_OPSIZE;
388 else if (HasAdSizePrefix)
389 insnContext = IC_64BIT_ADSIZE;
390 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
391 insnContext = IC_64BIT_REXW_XS;
392 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
393 insnContext = IC_64BIT_REXW_XD;
394 else if (OpPrefix == X86Local::XD)
395 insnContext = IC_64BIT_XD;
396 else if (OpPrefix == X86Local::XS)
397 insnContext = IC_64BIT_XS;
398 else if (HasREX_WPrefix)
399 insnContext = IC_64BIT_REXW;
401 insnContext = IC_64BIT;
403 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
404 insnContext = IC_XD_OPSIZE;
405 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
406 insnContext = IC_XS_OPSIZE;
407 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
408 insnContext = IC_OPSIZE;
409 else if (HasAdSizePrefix)
410 insnContext = IC_ADSIZE;
411 else if (OpPrefix == X86Local::XD)
413 else if (OpPrefix == X86Local::XS || HasREPPrefix)
422 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
423 unsigned &physicalOperandIndex,
424 unsigned &numPhysicalOperands,
425 const unsigned *operandMapping,
426 OperandEncoding (*encodingFromString)
430 if (physicalOperandIndex >= numPhysicalOperands)
433 assert(physicalOperandIndex < numPhysicalOperands);
436 while (operandMapping[operandIndex] != operandIndex) {
437 Spec->operands[operandIndex].encoding = ENCODING_DUP;
438 Spec->operands[operandIndex].type =
439 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
443 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
445 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
447 Spec->operands[operandIndex].type = typeFromString(typeName,
448 HasREX_WPrefix, OpSize);
451 ++physicalOperandIndex;
454 void RecognizableInstr::emitInstructionSpecifier() {
457 Spec->insnContext = insnContext();
459 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
461 unsigned numOperands = OperandList.size();
462 unsigned numPhysicalOperands = 0;
464 // operandMapping maps from operands in OperandList to their originals.
465 // If operandMapping[i] != i, then the entry is a duplicate.
466 unsigned operandMapping[X86_MAX_OPERANDS];
467 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
469 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
470 if (OperandList[operandIndex].Constraints.size()) {
471 const CGIOperandList::ConstraintInfo &Constraint =
472 OperandList[operandIndex].Constraints[0];
473 if (Constraint.isTied()) {
474 operandMapping[operandIndex] = operandIndex;
475 operandMapping[Constraint.getTiedOperand()] = operandIndex;
477 ++numPhysicalOperands;
478 operandMapping[operandIndex] = operandIndex;
481 ++numPhysicalOperands;
482 operandMapping[operandIndex] = operandIndex;
486 #define HANDLE_OPERAND(class) \
487 handleOperand(false, \
489 physicalOperandIndex, \
490 numPhysicalOperands, \
492 class##EncodingFromString);
494 #define HANDLE_OPTIONAL(class) \
495 handleOperand(true, \
497 physicalOperandIndex, \
498 numPhysicalOperands, \
500 class##EncodingFromString);
502 // operandIndex should always be < numOperands
503 unsigned operandIndex = 0;
504 // physicalOperandIndex should always be < numPhysicalOperands
505 unsigned physicalOperandIndex = 0;
508 default: llvm_unreachable("Unhandled form");
509 case X86Local::RawFrmSrc:
510 HANDLE_OPERAND(relocation);
512 case X86Local::RawFrmDst:
513 HANDLE_OPERAND(relocation);
515 case X86Local::RawFrmDstSrc:
516 HANDLE_OPERAND(relocation);
517 HANDLE_OPERAND(relocation);
519 case X86Local::RawFrm:
520 // Operand 1 (optional) is an address or immediate.
521 // Operand 2 (optional) is an immediate.
522 assert(numPhysicalOperands <= 2 &&
523 "Unexpected number of operands for RawFrm");
524 HANDLE_OPTIONAL(relocation)
525 HANDLE_OPTIONAL(immediate)
527 case X86Local::RawFrmMemOffs:
528 // Operand 1 is an address.
529 HANDLE_OPERAND(relocation);
531 case X86Local::AddRegFrm:
532 // Operand 1 is added to the opcode.
533 // Operand 2 (optional) is an address.
534 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
535 "Unexpected number of operands for AddRegFrm");
536 HANDLE_OPERAND(opcodeModifier)
537 HANDLE_OPTIONAL(relocation)
539 case X86Local::MRMDestReg:
540 // Operand 1 is a register operand in the R/M field.
541 // Operand 2 is a register operand in the Reg/Opcode field.
542 // - In AVX, there is a register operand in the VEX.vvvv field here -
543 // Operand 3 (optional) is an immediate.
545 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
546 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
548 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
549 "Unexpected number of operands for MRMDestRegFrm");
551 HANDLE_OPERAND(rmRegister)
554 // FIXME: In AVX, the register below becomes the one encoded
555 // in ModRMVEX and the one above the one in the VEX.VVVV field
556 HANDLE_OPERAND(vvvvRegister)
558 HANDLE_OPERAND(roRegister)
559 HANDLE_OPTIONAL(immediate)
561 case X86Local::MRMDestMem:
562 // Operand 1 is a memory operand (possibly SIB-extended)
563 // Operand 2 is a register operand in the Reg/Opcode field.
564 // - In AVX, there is a register operand in the VEX.vvvv field here -
565 // Operand 3 (optional) is an immediate.
567 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
568 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
570 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
571 "Unexpected number of operands for MRMDestMemFrm");
572 HANDLE_OPERAND(memory)
575 HANDLE_OPERAND(writemaskRegister)
578 // FIXME: In AVX, the register below becomes the one encoded
579 // in ModRMVEX and the one above the one in the VEX.VVVV field
580 HANDLE_OPERAND(vvvvRegister)
582 HANDLE_OPERAND(roRegister)
583 HANDLE_OPTIONAL(immediate)
585 case X86Local::MRMSrcReg:
586 // Operand 1 is a register operand in the Reg/Opcode field.
587 // Operand 2 is a register operand in the R/M field.
588 // - In AVX, there is a register operand in the VEX.vvvv field here -
589 // Operand 3 (optional) is an immediate.
590 // Operand 4 (optional) is an immediate.
592 if (HasVEX_4V || HasVEX_4VOp3)
593 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
594 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
596 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
597 "Unexpected number of operands for MRMSrcRegFrm");
599 HANDLE_OPERAND(roRegister)
602 HANDLE_OPERAND(writemaskRegister)
605 // FIXME: In AVX, the register below becomes the one encoded
606 // in ModRMVEX and the one above the one in the VEX.VVVV field
607 HANDLE_OPERAND(vvvvRegister)
610 HANDLE_OPERAND(immediate)
612 HANDLE_OPERAND(rmRegister)
615 HANDLE_OPERAND(vvvvRegister)
617 if (!HasMemOp4Prefix)
618 HANDLE_OPTIONAL(immediate)
619 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
620 HANDLE_OPTIONAL(immediate)
622 case X86Local::MRMSrcMem:
623 // Operand 1 is a register operand in the Reg/Opcode field.
624 // Operand 2 is a memory operand (possibly SIB-extended)
625 // - In AVX, there is a register operand in the VEX.vvvv field here -
626 // Operand 3 (optional) is an immediate.
628 if (HasVEX_4V || HasVEX_4VOp3)
629 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
630 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
632 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
633 "Unexpected number of operands for MRMSrcMemFrm");
635 HANDLE_OPERAND(roRegister)
638 HANDLE_OPERAND(writemaskRegister)
641 // FIXME: In AVX, the register below becomes the one encoded
642 // in ModRMVEX and the one above the one in the VEX.VVVV field
643 HANDLE_OPERAND(vvvvRegister)
646 HANDLE_OPERAND(immediate)
648 HANDLE_OPERAND(memory)
651 HANDLE_OPERAND(vvvvRegister)
653 if (!HasMemOp4Prefix)
654 HANDLE_OPTIONAL(immediate)
655 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
657 case X86Local::MRMXr:
658 case X86Local::MRM0r:
659 case X86Local::MRM1r:
660 case X86Local::MRM2r:
661 case X86Local::MRM3r:
662 case X86Local::MRM4r:
663 case X86Local::MRM5r:
664 case X86Local::MRM6r:
665 case X86Local::MRM7r:
667 // Operand 1 is a register operand in the R/M field.
668 // Operand 2 (optional) is an immediate or relocation.
669 // Operand 3 (optional) is an immediate.
670 unsigned kOp = (HasEVEX_K) ? 1:0;
671 unsigned Op4v = (HasVEX_4V) ? 1:0;
672 if (numPhysicalOperands > 3 + kOp + Op4v)
673 llvm_unreachable("Unexpected number of operands for MRMnr");
676 HANDLE_OPERAND(vvvvRegister)
679 HANDLE_OPERAND(writemaskRegister)
680 HANDLE_OPTIONAL(rmRegister)
681 HANDLE_OPTIONAL(relocation)
682 HANDLE_OPTIONAL(immediate)
684 case X86Local::MRMXm:
685 case X86Local::MRM0m:
686 case X86Local::MRM1m:
687 case X86Local::MRM2m:
688 case X86Local::MRM3m:
689 case X86Local::MRM4m:
690 case X86Local::MRM5m:
691 case X86Local::MRM6m:
692 case X86Local::MRM7m:
694 // Operand 1 is a memory operand (possibly SIB-extended)
695 // Operand 2 (optional) is an immediate or relocation.
696 unsigned kOp = (HasEVEX_K) ? 1:0;
697 unsigned Op4v = (HasVEX_4V) ? 1:0;
698 if (numPhysicalOperands < 1 + kOp + Op4v ||
699 numPhysicalOperands > 2 + kOp + Op4v)
700 llvm_unreachable("Unexpected number of operands for MRMnm");
703 HANDLE_OPERAND(vvvvRegister)
705 HANDLE_OPERAND(writemaskRegister)
706 HANDLE_OPERAND(memory)
707 HANDLE_OPTIONAL(relocation)
709 case X86Local::RawFrmImm8:
710 // operand 1 is a 16-bit immediate
711 // operand 2 is an 8-bit immediate
712 assert(numPhysicalOperands == 2 &&
713 "Unexpected number of operands for X86Local::RawFrmImm8");
714 HANDLE_OPERAND(immediate)
715 HANDLE_OPERAND(immediate)
717 case X86Local::RawFrmImm16:
718 // operand 1 is a 16-bit immediate
719 // operand 2 is a 16-bit immediate
720 HANDLE_OPERAND(immediate)
721 HANDLE_OPERAND(immediate)
723 case X86Local::MRM_F8:
724 if (Opcode == 0xc6) {
725 assert(numPhysicalOperands == 1 &&
726 "Unexpected number of operands for X86Local::MRM_F8");
727 HANDLE_OPERAND(immediate)
728 } else if (Opcode == 0xc7) {
729 assert(numPhysicalOperands == 1 &&
730 "Unexpected number of operands for X86Local::MRM_F8");
731 HANDLE_OPERAND(relocation)
734 case X86Local::MRM_C1:
735 case X86Local::MRM_C2:
736 case X86Local::MRM_C3:
737 case X86Local::MRM_C4:
738 case X86Local::MRM_C8:
739 case X86Local::MRM_C9:
740 case X86Local::MRM_CA:
741 case X86Local::MRM_CB:
742 case X86Local::MRM_E8:
743 case X86Local::MRM_F0:
744 case X86Local::MRM_F9:
745 case X86Local::MRM_D0:
746 case X86Local::MRM_D1:
747 case X86Local::MRM_D4:
748 case X86Local::MRM_D5:
749 case X86Local::MRM_D6:
750 case X86Local::MRM_D8:
751 case X86Local::MRM_D9:
752 case X86Local::MRM_DA:
753 case X86Local::MRM_DB:
754 case X86Local::MRM_DC:
755 case X86Local::MRM_DD:
756 case X86Local::MRM_DE:
757 case X86Local::MRM_DF:
762 #undef HANDLE_OPERAND
763 #undef HANDLE_OPTIONAL
766 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
767 // Special cases where the LLVM tables are not complete
769 #define MAP(from, to) \
770 case X86Local::MRM_##from: \
771 filter = new ExactFilter(0x##from); \
774 OpcodeType opcodeType = (OpcodeType)-1;
776 ModRMFilter* filter = NULL;
777 uint8_t opcodeToSet = 0;
780 default: llvm_unreachable("Invalid map!");
791 default: llvm_unreachable("Unexpected map!");
792 case X86Local::OB: opcodeType = ONEBYTE; break;
793 case X86Local::TB: opcodeType = TWOBYTE; break;
794 case X86Local::T8: opcodeType = THREEBYTE_38; break;
795 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
796 case X86Local::A6: opcodeType = THREEBYTE_A6; break;
797 case X86Local::A7: opcodeType = THREEBYTE_A7; break;
798 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
799 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
800 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
805 filter = new DumbFilter();
807 case X86Local::MRMDestReg: case X86Local::MRMDestMem:
808 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
809 case X86Local::MRMXr: case X86Local::MRMXm:
810 filter = new ModFilter(isRegFormat(Form));
812 case X86Local::MRM0r: case X86Local::MRM1r:
813 case X86Local::MRM2r: case X86Local::MRM3r:
814 case X86Local::MRM4r: case X86Local::MRM5r:
815 case X86Local::MRM6r: case X86Local::MRM7r:
816 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
818 case X86Local::MRM0m: case X86Local::MRM1m:
819 case X86Local::MRM2m: case X86Local::MRM3m:
820 case X86Local::MRM4m: case X86Local::MRM5m:
821 case X86Local::MRM6m: case X86Local::MRM7m:
822 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
827 opcodeToSet = Opcode;
837 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
838 assert(Form == X86Local::RawFrm);
839 opcodeType = ONEBYTE;
840 filter = new ExactFilter(Opcode);
841 opcodeToSet = 0xd8 + (OpMap - X86Local::D8);
845 assert(opcodeType != (OpcodeType)-1 &&
846 "Opcode type not set");
847 assert(filter && "Filter not set");
849 if (Form == X86Local::AddRegFrm) {
850 assert(((opcodeToSet & 7) == 0) &&
851 "ADDREG_FRM opcode not aligned");
853 uint8_t currentOpcode;
855 for (currentOpcode = opcodeToSet;
856 currentOpcode < opcodeToSet + 8;
858 tables.setTableFields(opcodeType,
862 UID, Is32Bit, IgnoresVEX_L);
864 tables.setTableFields(opcodeType,
868 UID, Is32Bit, IgnoresVEX_L);
876 #define TYPE(str, type) if (s == str) return type;
877 OperandType RecognizableInstr::typeFromString(const std::string &s,
881 // For instructions with a REX_W prefix, a declared 32-bit register encoding
883 TYPE("GR32", TYPE_R32)
885 if(OpSize == X86Local::OpSize16) {
886 // For OpSize16 instructions, a declared 16-bit register or
887 // immediate encoding is special.
888 TYPE("GR16", TYPE_Rv)
889 TYPE("i16imm", TYPE_IMMv)
890 } else if(OpSize == X86Local::OpSize32) {
891 // For OpSize32 instructions, a declared 32-bit register or
892 // immediate encoding is special.
893 TYPE("GR32", TYPE_Rv)
895 TYPE("i16mem", TYPE_Mv)
896 TYPE("i16imm", TYPE_IMM16)
897 TYPE("i16i8imm", TYPE_IMMv)
898 TYPE("GR16", TYPE_R16)
899 TYPE("i32mem", TYPE_Mv)
900 TYPE("i32imm", TYPE_IMMv)
901 TYPE("i32i8imm", TYPE_IMM32)
902 TYPE("u32u8imm", TYPE_IMM32)
903 TYPE("GR32", TYPE_R32)
904 TYPE("GR32orGR64", TYPE_R32)
905 TYPE("i64mem", TYPE_Mv)
906 TYPE("i64i32imm", TYPE_IMM64)
907 TYPE("i64i8imm", TYPE_IMM64)
908 TYPE("GR64", TYPE_R64)
909 TYPE("i8mem", TYPE_M8)
910 TYPE("i8imm", TYPE_IMM8)
912 TYPE("VR128", TYPE_XMM128)
913 TYPE("VR128X", TYPE_XMM128)
914 TYPE("f128mem", TYPE_M128)
915 TYPE("f256mem", TYPE_M256)
916 TYPE("f512mem", TYPE_M512)
917 TYPE("FR64", TYPE_XMM64)
918 TYPE("FR64X", TYPE_XMM64)
919 TYPE("f64mem", TYPE_M64FP)
920 TYPE("sdmem", TYPE_M64FP)
921 TYPE("FR32", TYPE_XMM32)
922 TYPE("FR32X", TYPE_XMM32)
923 TYPE("f32mem", TYPE_M32FP)
924 TYPE("ssmem", TYPE_M32FP)
926 TYPE("i128mem", TYPE_M128)
927 TYPE("i256mem", TYPE_M256)
928 TYPE("i512mem", TYPE_M512)
929 TYPE("i64i32imm_pcrel", TYPE_REL64)
930 TYPE("i16imm_pcrel", TYPE_REL16)
931 TYPE("i32imm_pcrel", TYPE_REL32)
932 TYPE("SSECC", TYPE_IMM3)
933 TYPE("AVXCC", TYPE_IMM5)
934 TYPE("AVX512RC", TYPE_IMM32)
935 TYPE("brtarget", TYPE_RELv)
936 TYPE("uncondbrtarget", TYPE_RELv)
937 TYPE("brtarget8", TYPE_REL8)
938 TYPE("f80mem", TYPE_M80FP)
939 TYPE("lea32mem", TYPE_LEA)
940 TYPE("lea64_32mem", TYPE_LEA)
941 TYPE("lea64mem", TYPE_LEA)
942 TYPE("VR64", TYPE_MM64)
943 TYPE("i64imm", TYPE_IMMv)
944 TYPE("opaque32mem", TYPE_M1616)
945 TYPE("opaque48mem", TYPE_M1632)
946 TYPE("opaque80mem", TYPE_M1664)
947 TYPE("opaque512mem", TYPE_M512)
948 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
949 TYPE("DEBUG_REG", TYPE_DEBUGREG)
950 TYPE("CONTROL_REG", TYPE_CONTROLREG)
951 TYPE("srcidx8", TYPE_SRCIDX8)
952 TYPE("srcidx16", TYPE_SRCIDX16)
953 TYPE("srcidx32", TYPE_SRCIDX32)
954 TYPE("srcidx64", TYPE_SRCIDX64)
955 TYPE("dstidx8", TYPE_DSTIDX8)
956 TYPE("dstidx16", TYPE_DSTIDX16)
957 TYPE("dstidx32", TYPE_DSTIDX32)
958 TYPE("dstidx64", TYPE_DSTIDX64)
959 TYPE("offset8", TYPE_MOFFS8)
960 TYPE("offset16", TYPE_MOFFS16)
961 TYPE("offset32", TYPE_MOFFS32)
962 TYPE("offset64", TYPE_MOFFS64)
963 TYPE("VR256", TYPE_XMM256)
964 TYPE("VR256X", TYPE_XMM256)
965 TYPE("VR512", TYPE_XMM512)
966 TYPE("VK1", TYPE_VK1)
967 TYPE("VK1WM", TYPE_VK1)
968 TYPE("VK8", TYPE_VK8)
969 TYPE("VK8WM", TYPE_VK8)
970 TYPE("VK16", TYPE_VK16)
971 TYPE("VK16WM", TYPE_VK16)
972 TYPE("GR16_NOAX", TYPE_Rv)
973 TYPE("GR32_NOAX", TYPE_Rv)
974 TYPE("GR64_NOAX", TYPE_R64)
975 TYPE("vx32mem", TYPE_M32)
976 TYPE("vy32mem", TYPE_M32)
977 TYPE("vz32mem", TYPE_M32)
978 TYPE("vx64mem", TYPE_M64)
979 TYPE("vy64mem", TYPE_M64)
980 TYPE("vy64xmem", TYPE_M64)
981 TYPE("vz64mem", TYPE_M64)
982 errs() << "Unhandled type string " << s << "\n";
983 llvm_unreachable("Unhandled type string");
987 #define ENCODING(str, encoding) if (s == str) return encoding;
989 RecognizableInstr::immediateEncodingFromString(const std::string &s,
991 if(OpSize != X86Local::OpSize16) {
992 // For instructions without an OpSize prefix, a declared 16-bit register or
993 // immediate encoding is special.
994 ENCODING("i16imm", ENCODING_IW)
996 ENCODING("i32i8imm", ENCODING_IB)
997 ENCODING("u32u8imm", ENCODING_IB)
998 ENCODING("SSECC", ENCODING_IB)
999 ENCODING("AVXCC", ENCODING_IB)
1000 ENCODING("AVX512RC", ENCODING_IB)
1001 ENCODING("i16imm", ENCODING_Iv)
1002 ENCODING("i16i8imm", ENCODING_IB)
1003 ENCODING("i32imm", ENCODING_Iv)
1004 ENCODING("i64i32imm", ENCODING_ID)
1005 ENCODING("i64i8imm", ENCODING_IB)
1006 ENCODING("i8imm", ENCODING_IB)
1007 // This is not a typo. Instructions like BLENDVPD put
1008 // register IDs in 8-bit immediates nowadays.
1009 ENCODING("FR32", ENCODING_IB)
1010 ENCODING("FR64", ENCODING_IB)
1011 ENCODING("VR128", ENCODING_IB)
1012 ENCODING("VR256", ENCODING_IB)
1013 ENCODING("FR32X", ENCODING_IB)
1014 ENCODING("FR64X", ENCODING_IB)
1015 ENCODING("VR128X", ENCODING_IB)
1016 ENCODING("VR256X", ENCODING_IB)
1017 ENCODING("VR512", ENCODING_IB)
1018 errs() << "Unhandled immediate encoding " << s << "\n";
1019 llvm_unreachable("Unhandled immediate encoding");
1023 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1025 ENCODING("RST", ENCODING_FP)
1026 ENCODING("GR16", ENCODING_RM)
1027 ENCODING("GR32", ENCODING_RM)
1028 ENCODING("GR32orGR64", ENCODING_RM)
1029 ENCODING("GR64", ENCODING_RM)
1030 ENCODING("GR8", ENCODING_RM)
1031 ENCODING("VR128", ENCODING_RM)
1032 ENCODING("VR128X", ENCODING_RM)
1033 ENCODING("FR64", ENCODING_RM)
1034 ENCODING("FR32", ENCODING_RM)
1035 ENCODING("FR64X", ENCODING_RM)
1036 ENCODING("FR32X", ENCODING_RM)
1037 ENCODING("VR64", ENCODING_RM)
1038 ENCODING("VR256", ENCODING_RM)
1039 ENCODING("VR256X", ENCODING_RM)
1040 ENCODING("VR512", ENCODING_RM)
1041 ENCODING("VK1", ENCODING_RM)
1042 ENCODING("VK8", ENCODING_RM)
1043 ENCODING("VK16", ENCODING_RM)
1044 errs() << "Unhandled R/M register encoding " << s << "\n";
1045 llvm_unreachable("Unhandled R/M register encoding");
1049 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1051 ENCODING("GR16", ENCODING_REG)
1052 ENCODING("GR32", ENCODING_REG)
1053 ENCODING("GR32orGR64", ENCODING_REG)
1054 ENCODING("GR64", ENCODING_REG)
1055 ENCODING("GR8", ENCODING_REG)
1056 ENCODING("VR128", ENCODING_REG)
1057 ENCODING("FR64", ENCODING_REG)
1058 ENCODING("FR32", ENCODING_REG)
1059 ENCODING("VR64", ENCODING_REG)
1060 ENCODING("SEGMENT_REG", ENCODING_REG)
1061 ENCODING("DEBUG_REG", ENCODING_REG)
1062 ENCODING("CONTROL_REG", ENCODING_REG)
1063 ENCODING("VR256", ENCODING_REG)
1064 ENCODING("VR256X", ENCODING_REG)
1065 ENCODING("VR128X", ENCODING_REG)
1066 ENCODING("FR64X", ENCODING_REG)
1067 ENCODING("FR32X", ENCODING_REG)
1068 ENCODING("VR512", ENCODING_REG)
1069 ENCODING("VK1", ENCODING_REG)
1070 ENCODING("VK8", ENCODING_REG)
1071 ENCODING("VK16", ENCODING_REG)
1072 ENCODING("VK1WM", ENCODING_REG)
1073 ENCODING("VK8WM", ENCODING_REG)
1074 ENCODING("VK16WM", ENCODING_REG)
1075 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1076 llvm_unreachable("Unhandled reg/opcode register encoding");
1080 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1082 ENCODING("GR32", ENCODING_VVVV)
1083 ENCODING("GR64", ENCODING_VVVV)
1084 ENCODING("FR32", ENCODING_VVVV)
1085 ENCODING("FR64", ENCODING_VVVV)
1086 ENCODING("VR128", ENCODING_VVVV)
1087 ENCODING("VR256", ENCODING_VVVV)
1088 ENCODING("FR32X", ENCODING_VVVV)
1089 ENCODING("FR64X", ENCODING_VVVV)
1090 ENCODING("VR128X", ENCODING_VVVV)
1091 ENCODING("VR256X", ENCODING_VVVV)
1092 ENCODING("VR512", ENCODING_VVVV)
1093 ENCODING("VK1", ENCODING_VVVV)
1094 ENCODING("VK8", ENCODING_VVVV)
1095 ENCODING("VK16", ENCODING_VVVV)
1096 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1097 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1101 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1103 ENCODING("VK1WM", ENCODING_WRITEMASK)
1104 ENCODING("VK8WM", ENCODING_WRITEMASK)
1105 ENCODING("VK16WM", ENCODING_WRITEMASK)
1106 errs() << "Unhandled mask register encoding " << s << "\n";
1107 llvm_unreachable("Unhandled mask register encoding");
1111 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1113 ENCODING("i16mem", ENCODING_RM)
1114 ENCODING("i32mem", ENCODING_RM)
1115 ENCODING("i64mem", ENCODING_RM)
1116 ENCODING("i8mem", ENCODING_RM)
1117 ENCODING("ssmem", ENCODING_RM)
1118 ENCODING("sdmem", ENCODING_RM)
1119 ENCODING("f128mem", ENCODING_RM)
1120 ENCODING("f256mem", ENCODING_RM)
1121 ENCODING("f512mem", ENCODING_RM)
1122 ENCODING("f64mem", ENCODING_RM)
1123 ENCODING("f32mem", ENCODING_RM)
1124 ENCODING("i128mem", ENCODING_RM)
1125 ENCODING("i256mem", ENCODING_RM)
1126 ENCODING("i512mem", ENCODING_RM)
1127 ENCODING("f80mem", ENCODING_RM)
1128 ENCODING("lea32mem", ENCODING_RM)
1129 ENCODING("lea64_32mem", ENCODING_RM)
1130 ENCODING("lea64mem", ENCODING_RM)
1131 ENCODING("opaque32mem", ENCODING_RM)
1132 ENCODING("opaque48mem", ENCODING_RM)
1133 ENCODING("opaque80mem", ENCODING_RM)
1134 ENCODING("opaque512mem", ENCODING_RM)
1135 ENCODING("vx32mem", ENCODING_RM)
1136 ENCODING("vy32mem", ENCODING_RM)
1137 ENCODING("vz32mem", ENCODING_RM)
1138 ENCODING("vx64mem", ENCODING_RM)
1139 ENCODING("vy64mem", ENCODING_RM)
1140 ENCODING("vy64xmem", ENCODING_RM)
1141 ENCODING("vz64mem", ENCODING_RM)
1142 errs() << "Unhandled memory encoding " << s << "\n";
1143 llvm_unreachable("Unhandled memory encoding");
1147 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1149 if(OpSize != X86Local::OpSize16) {
1150 // For instructions without an OpSize prefix, a declared 16-bit register or
1151 // immediate encoding is special.
1152 ENCODING("i16imm", ENCODING_IW)
1154 ENCODING("i16imm", ENCODING_Iv)
1155 ENCODING("i16i8imm", ENCODING_IB)
1156 ENCODING("i32imm", ENCODING_Iv)
1157 ENCODING("i32i8imm", ENCODING_IB)
1158 ENCODING("i64i32imm", ENCODING_ID)
1159 ENCODING("i64i8imm", ENCODING_IB)
1160 ENCODING("i8imm", ENCODING_IB)
1161 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1162 ENCODING("i16imm_pcrel", ENCODING_IW)
1163 ENCODING("i32imm_pcrel", ENCODING_ID)
1164 ENCODING("brtarget", ENCODING_Iv)
1165 ENCODING("brtarget8", ENCODING_IB)
1166 ENCODING("i64imm", ENCODING_IO)
1167 ENCODING("offset8", ENCODING_Ia)
1168 ENCODING("offset16", ENCODING_Ia)
1169 ENCODING("offset32", ENCODING_Ia)
1170 ENCODING("offset64", ENCODING_Ia)
1171 ENCODING("srcidx8", ENCODING_SI)
1172 ENCODING("srcidx16", ENCODING_SI)
1173 ENCODING("srcidx32", ENCODING_SI)
1174 ENCODING("srcidx64", ENCODING_SI)
1175 ENCODING("dstidx8", ENCODING_DI)
1176 ENCODING("dstidx16", ENCODING_DI)
1177 ENCODING("dstidx32", ENCODING_DI)
1178 ENCODING("dstidx64", ENCODING_DI)
1179 errs() << "Unhandled relocation encoding " << s << "\n";
1180 llvm_unreachable("Unhandled relocation encoding");
1184 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1186 ENCODING("GR32", ENCODING_Rv)
1187 ENCODING("GR64", ENCODING_RO)
1188 ENCODING("GR16", ENCODING_Rv)
1189 ENCODING("GR8", ENCODING_RB)
1190 ENCODING("GR16_NOAX", ENCODING_Rv)
1191 ENCODING("GR32_NOAX", ENCODING_Rv)
1192 ENCODING("GR64_NOAX", ENCODING_RO)
1193 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1194 llvm_unreachable("Unhandled opcode modifier encoding");