1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
34 // A clone of X86 since we can't depend on something that is generated.
44 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
45 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
46 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
47 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
50 #define MAP(from, to) MRM_##from = to,
59 D8 = 3, D9 = 4, DA = 5, DB = 6,
60 DC = 7, DD = 8, DE = 9, DF = 10,
63 P_0F_AE = 16, P_0F_01 = 17
67 // If rows are added to the opcode extension tables, then corresponding entries
68 // must be added here.
70 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
71 // that byte to ONE_BYTE_EXTENSION_TABLES.
73 // If the row corresponds to two bytes where the first is 0f, add an entry for
74 // the second byte to TWO_BYTE_EXTENSION_TABLES.
76 // If the row corresponds to some other set of bytes, you will need to modify
77 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
78 // to the X86 TD files, except in two cases: if the first two bytes of such a
79 // new combination are 0f 38 or 0f 3a, you just have to add maps called
80 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
81 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
82 // in RecognizableInstr::emitDecodePath().
84 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(fe) \
103 #define TWO_BYTE_EXTENSION_TABLES \
104 EXTENSION_TABLE(00) \
105 EXTENSION_TABLE(01) \
106 EXTENSION_TABLE(18) \
107 EXTENSION_TABLE(71) \
108 EXTENSION_TABLE(72) \
109 EXTENSION_TABLE(73) \
110 EXTENSION_TABLE(ae) \
111 EXTENSION_TABLE(b9) \
112 EXTENSION_TABLE(ba) \
115 using namespace X86Disassembler;
117 /// needsModRMForDecode - Indicates whether a particular instruction requires a
118 /// ModR/M byte for the instruction to be properly decoded. For example, a
119 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
122 /// @param form - The form of the instruction.
123 /// @return - true if the form implies that a ModR/M byte is required, false
125 static bool needsModRMForDecode(uint8_t form) {
126 if (form == X86Local::MRMDestReg ||
127 form == X86Local::MRMDestMem ||
128 form == X86Local::MRMSrcReg ||
129 form == X86Local::MRMSrcMem ||
130 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
131 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
137 /// isRegFormat - Indicates whether a particular form requires the Mod field of
138 /// the ModR/M byte to be 0b11.
140 /// @param form - The form of the instruction.
141 /// @return - true if the form implies that Mod must be 0b11, false
143 static bool isRegFormat(uint8_t form) {
144 if (form == X86Local::MRMDestReg ||
145 form == X86Local::MRMSrcReg ||
146 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
152 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
153 /// Useful for switch statements and the like.
155 /// @param init - A reference to the BitsInit to be decoded.
156 /// @return - The field, with the first bit in the BitsInit as the lowest
158 static uint8_t byteFromBitsInit(BitsInit &init) {
159 int width = init.getNumBits();
161 assert(width <= 8 && "Field is too large for uint8_t!");
168 for (index = 0; index < width; index++) {
169 if (static_cast<BitInit*>(init.getBit(index))->getValue())
178 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
179 /// name of the field.
181 /// @param rec - The record from which to extract the value.
182 /// @param name - The name of the field in the record.
183 /// @return - The field, as translated by byteFromBitsInit().
184 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
185 BitsInit* bits = rec->getValueAsBitsInit(name);
186 return byteFromBitsInit(*bits);
189 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
190 const CodeGenInstruction &insn,
195 Name = Rec->getName();
196 Spec = &tables.specForUID(UID);
198 if (!Rec->isSubClassOf("X86Inst")) {
199 ShouldBeEmitted = false;
203 Prefix = byteFromRec(Rec, "Prefix");
204 Opcode = byteFromRec(Rec, "Opcode");
205 Form = byteFromRec(Rec, "FormBits");
206 SegOvr = byteFromRec(Rec, "SegOvrBits");
208 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
209 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
210 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
211 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
213 Name = Rec->getName();
214 AsmString = Rec->getValueAsString("AsmString");
216 Operands = &insn.OperandList;
218 IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos);
219 HasFROperands = false;
221 ShouldBeEmitted = true;
224 void RecognizableInstr::processInstr(DisassemblerTables &tables,
225 const CodeGenInstruction &insn,
228 RecognizableInstr recogInstr(tables, insn, uid);
230 recogInstr.emitInstructionSpecifier(tables);
232 if (recogInstr.shouldBeEmitted())
233 recogInstr.emitDecodePath(tables);
236 InstructionContext RecognizableInstr::insnContext() const {
237 InstructionContext insnContext;
239 if (Name.find("64") != Name.npos || HasREX_WPrefix) {
240 if (HasREX_WPrefix && HasOpSizePrefix)
241 insnContext = IC_64BIT_REXW_OPSIZE;
242 else if (HasOpSizePrefix)
243 insnContext = IC_64BIT_OPSIZE;
244 else if (HasREX_WPrefix && Prefix == X86Local::XS)
245 insnContext = IC_64BIT_REXW_XS;
246 else if (HasREX_WPrefix && Prefix == X86Local::XD)
247 insnContext = IC_64BIT_REXW_XD;
248 else if (Prefix == X86Local::XD)
249 insnContext = IC_64BIT_XD;
250 else if (Prefix == X86Local::XS)
251 insnContext = IC_64BIT_XS;
252 else if (HasREX_WPrefix)
253 insnContext = IC_64BIT_REXW;
255 insnContext = IC_64BIT;
258 insnContext = IC_OPSIZE;
259 else if (Prefix == X86Local::XD)
261 else if (Prefix == X86Local::XS)
270 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
271 // Filter out intrinsics
273 if (!Rec->isSubClassOf("X86Inst"))
274 return FILTER_STRONG;
276 if (Form == X86Local::Pseudo ||
278 return FILTER_STRONG;
280 // Filter out instructions with a LOCK prefix;
281 // prefer forms that do not have the prefix
285 // Filter out artificial instructions
287 if (Name.find("TAILJMP") != Name.npos ||
288 Name.find("_Int") != Name.npos ||
289 Name.find("_int") != Name.npos ||
290 Name.find("Int_") != Name.npos ||
291 Name.find("_NOREX") != Name.npos ||
292 Name.find("EH_RETURN") != Name.npos ||
293 Name.find("V_SET") != Name.npos ||
294 Name.find("LOCK_") != Name.npos ||
295 Name.find("WIN") != Name.npos)
296 return FILTER_STRONG;
300 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
302 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
305 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
307 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
309 if (Name.find("Fs") != Name.npos)
311 if (Name == "MOVLPDrr" ||
312 Name == "MOVLPSrr" ||
318 Name == "MOVSX16rm8" ||
319 Name == "MOVSX16rr8" ||
320 Name == "MOVZX16rm8" ||
321 Name == "MOVZX16rr8" ||
322 Name == "PUSH32i16" ||
323 Name == "PUSH64i16" ||
324 Name == "MOVPQI2QImr" ||
329 Name == "MMX_MOVD64rrv164" ||
330 Name == "CRC32m16" ||
331 Name == "MOV64ri64i32" ||
335 // Filter out instructions with segment override prefixes.
336 // They're too messy to handle now and we'll special case them if needed.
339 return FILTER_STRONG;
341 // Filter out instructions that can't be printed.
343 if (AsmString.size() == 0)
344 return FILTER_STRONG;
346 // Filter out instructions with subreg operands.
348 if (AsmString.find("subreg") != AsmString.npos)
349 return FILTER_STRONG;
351 assert(Form != X86Local::MRMInitReg &&
352 "FORMAT_MRMINITREG instruction not skipped");
354 if (HasFROperands && Name.find("MOV") != Name.npos &&
355 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
356 (Name.find("to") != Name.npos)))
359 return FILTER_NORMAL;
362 void RecognizableInstr::handleOperand(
364 unsigned &operandIndex,
365 unsigned &physicalOperandIndex,
366 unsigned &numPhysicalOperands,
367 unsigned *operandMapping,
368 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
370 if (physicalOperandIndex >= numPhysicalOperands)
373 assert(physicalOperandIndex < numPhysicalOperands);
376 while (operandMapping[operandIndex] != operandIndex) {
377 Spec->operands[operandIndex].encoding = ENCODING_DUP;
378 Spec->operands[operandIndex].type =
379 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
383 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
385 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
387 Spec->operands[operandIndex].type = typeFromString(typeName,
393 ++physicalOperandIndex;
396 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
399 if (!Rec->isSubClassOf("X86Inst"))
404 Spec->filtered = true;
407 ShouldBeEmitted = false;
413 Spec->insnContext = insnContext();
415 const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
417 unsigned operandIndex;
418 unsigned numOperands = OperandList.size();
419 unsigned numPhysicalOperands = 0;
421 // operandMapping maps from operands in OperandList to their originals.
422 // If operandMapping[i] != i, then the entry is a duplicate.
423 unsigned operandMapping[X86_MAX_OPERANDS];
425 bool hasFROperands = false;
427 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
429 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
430 if (OperandList[operandIndex].Constraints.size()) {
431 const CodeGenInstruction::ConstraintInfo &Constraint =
432 OperandList[operandIndex].Constraints[0];
433 if (Constraint.isTied()) {
434 operandMapping[operandIndex] = Constraint.getTiedOperand();
436 ++numPhysicalOperands;
437 operandMapping[operandIndex] = operandIndex;
440 ++numPhysicalOperands;
441 operandMapping[operandIndex] = operandIndex;
444 const std::string &recName = OperandList[operandIndex].Rec->getName();
446 if (recName.find("FR") != recName.npos)
447 hasFROperands = true;
450 if (hasFROperands && Name.find("MOV") != Name.npos &&
451 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
452 (Name.find("to") != Name.npos)))
453 ShouldBeEmitted = false;
455 if (!ShouldBeEmitted)
458 #define HANDLE_OPERAND(class) \
459 handleOperand(false, \
461 physicalOperandIndex, \
462 numPhysicalOperands, \
464 class##EncodingFromString);
466 #define HANDLE_OPTIONAL(class) \
467 handleOperand(true, \
469 physicalOperandIndex, \
470 numPhysicalOperands, \
472 class##EncodingFromString);
474 // operandIndex should always be < numOperands
476 // physicalOperandIndex should always be < numPhysicalOperands
477 unsigned physicalOperandIndex = 0;
480 case X86Local::RawFrm:
481 // Operand 1 (optional) is an address or immediate.
482 // Operand 2 (optional) is an immediate.
483 assert(numPhysicalOperands <= 2 &&
484 "Unexpected number of operands for RawFrm");
485 HANDLE_OPTIONAL(relocation)
486 HANDLE_OPTIONAL(immediate)
488 case X86Local::AddRegFrm:
489 // Operand 1 is added to the opcode.
490 // Operand 2 (optional) is an address.
491 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
492 "Unexpected number of operands for AddRegFrm");
493 HANDLE_OPERAND(opcodeModifier)
494 HANDLE_OPTIONAL(relocation)
496 case X86Local::MRMDestReg:
497 // Operand 1 is a register operand in the R/M field.
498 // Operand 2 is a register operand in the Reg/Opcode field.
499 // Operand 3 (optional) is an immediate.
500 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
501 "Unexpected number of operands for MRMDestRegFrm");
502 HANDLE_OPERAND(rmRegister)
503 HANDLE_OPERAND(roRegister)
504 HANDLE_OPTIONAL(immediate)
506 case X86Local::MRMDestMem:
507 // Operand 1 is a memory operand (possibly SIB-extended)
508 // Operand 2 is a register operand in the Reg/Opcode field.
509 // Operand 3 (optional) is an immediate.
510 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
511 "Unexpected number of operands for MRMDestMemFrm");
512 HANDLE_OPERAND(memory)
513 HANDLE_OPERAND(roRegister)
514 HANDLE_OPTIONAL(immediate)
516 case X86Local::MRMSrcReg:
517 // Operand 1 is a register operand in the Reg/Opcode field.
518 // Operand 2 is a register operand in the R/M field.
519 // Operand 3 (optional) is an immediate.
520 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
521 "Unexpected number of operands for MRMSrcRegFrm");
522 HANDLE_OPERAND(roRegister)
523 HANDLE_OPERAND(rmRegister)
524 HANDLE_OPTIONAL(immediate)
526 case X86Local::MRMSrcMem:
527 // Operand 1 is a register operand in the Reg/Opcode field.
528 // Operand 2 is a memory operand (possibly SIB-extended)
529 // Operand 3 (optional) is an immediate.
530 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
531 "Unexpected number of operands for MRMSrcMemFrm");
532 HANDLE_OPERAND(roRegister)
533 HANDLE_OPERAND(memory)
534 HANDLE_OPTIONAL(immediate)
536 case X86Local::MRM0r:
537 case X86Local::MRM1r:
538 case X86Local::MRM2r:
539 case X86Local::MRM3r:
540 case X86Local::MRM4r:
541 case X86Local::MRM5r:
542 case X86Local::MRM6r:
543 case X86Local::MRM7r:
544 // Operand 1 is a register operand in the R/M field.
545 // Operand 2 (optional) is an immediate or relocation.
546 assert(numPhysicalOperands <= 2 &&
547 "Unexpected number of operands for MRMnRFrm");
548 HANDLE_OPTIONAL(rmRegister)
549 HANDLE_OPTIONAL(relocation)
551 case X86Local::MRM0m:
552 case X86Local::MRM1m:
553 case X86Local::MRM2m:
554 case X86Local::MRM3m:
555 case X86Local::MRM4m:
556 case X86Local::MRM5m:
557 case X86Local::MRM6m:
558 case X86Local::MRM7m:
559 // Operand 1 is a memory operand (possibly SIB-extended)
560 // Operand 2 (optional) is an immediate or relocation.
561 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
562 "Unexpected number of operands for MRMnMFrm");
563 HANDLE_OPERAND(memory)
564 HANDLE_OPTIONAL(relocation)
566 case X86Local::MRMInitReg:
571 #undef HANDLE_OPERAND
572 #undef HANDLE_OPTIONAL
575 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
576 // Special cases where the LLVM tables are not complete
578 #define MAP(from, to) \
579 case X86Local::MRM_##from: \
580 filter = new ExactFilter(0x##from); \
583 #define EXACTCASE(class, name, lastbyte) \
584 if (Name == name) { \
585 tables.setTableFields(class, \
588 ExactFilter(lastbyte), \
590 Spec->modifierBase = Opcode; \
594 EXACTCASE(TWOBYTE, "MONITOR", 0xc8)
595 EXACTCASE(TWOBYTE, "MWAIT", 0xc9)
596 EXACTCASE(TWOBYTE, "SWPGS", 0xf8)
597 EXACTCASE(TWOBYTE, "INVEPT", 0x80)
598 EXACTCASE(TWOBYTE, "INVVPID", 0x81)
599 //EXACTCASE(TWOBYTE, "VMCALL", 0xc1) - Handled by MRM_ form; safe to remove
600 EXACTCASE(TWOBYTE, "VMLAUNCH", 0xc2)
601 EXACTCASE(TWOBYTE, "VMRESUME", 0xc3)
602 EXACTCASE(TWOBYTE, "VMXOFF", 0xc4)
604 if (Name == "INVLPG") {
605 tables.setTableFields(TWOBYTE,
608 ExtendedFilter(false, 7),
610 Spec->modifierBase = Opcode;
614 OpcodeType opcodeType = (OpcodeType)-1;
616 ModRMFilter* filter = NULL;
617 uint8_t opcodeToSet = 0;
620 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
624 opcodeType = TWOBYTE;
627 #define EXTENSION_TABLE(n) case 0x##n:
628 TWO_BYTE_EXTENSION_TABLES
629 #undef EXTENSION_TABLE
632 llvm_unreachable("Unhandled two-byte extended opcode");
633 case X86Local::MRM0r:
634 case X86Local::MRM1r:
635 case X86Local::MRM2r:
636 case X86Local::MRM3r:
637 case X86Local::MRM4r:
638 case X86Local::MRM5r:
639 case X86Local::MRM6r:
640 case X86Local::MRM7r:
641 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
643 case X86Local::MRM0m:
644 case X86Local::MRM1m:
645 case X86Local::MRM2m:
646 case X86Local::MRM3m:
647 case X86Local::MRM4m:
648 case X86Local::MRM5m:
649 case X86Local::MRM6m:
650 case X86Local::MRM7m:
651 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
657 if (needsModRMForDecode(Form))
658 filter = new ModFilter(isRegFormat(Form));
660 filter = new DumbFilter();
664 opcodeToSet = Opcode;
667 opcodeType = THREEBYTE_38;
668 if (needsModRMForDecode(Form))
669 filter = new ModFilter(isRegFormat(Form));
671 filter = new DumbFilter();
672 opcodeToSet = Opcode;
675 opcodeType = THREEBYTE_3A;
676 if (needsModRMForDecode(Form))
677 filter = new ModFilter(isRegFormat(Form));
679 filter = new DumbFilter();
680 opcodeToSet = Opcode;
690 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
691 opcodeType = ONEBYTE;
692 if (Form == X86Local::AddRegFrm) {
693 Spec->modifierType = MODIFIER_MODRM;
694 Spec->modifierBase = Opcode;
695 filter = new AddRegEscapeFilter(Opcode);
697 filter = new EscapeFilter(true, Opcode);
699 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
702 opcodeType = ONEBYTE;
704 #define EXTENSION_TABLE(n) case 0x##n:
705 ONE_BYTE_EXTENSION_TABLES
706 #undef EXTENSION_TABLE
709 llvm_unreachable("Fell through the cracks of a single-byte "
711 case X86Local::MRM0r:
712 case X86Local::MRM1r:
713 case X86Local::MRM2r:
714 case X86Local::MRM3r:
715 case X86Local::MRM4r:
716 case X86Local::MRM5r:
717 case X86Local::MRM6r:
718 case X86Local::MRM7r:
719 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
721 case X86Local::MRM0m:
722 case X86Local::MRM1m:
723 case X86Local::MRM2m:
724 case X86Local::MRM3m:
725 case X86Local::MRM4m:
726 case X86Local::MRM5m:
727 case X86Local::MRM6m:
728 case X86Local::MRM7m:
729 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
742 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
745 if (needsModRMForDecode(Form))
746 filter = new ModFilter(isRegFormat(Form));
748 filter = new DumbFilter();
751 opcodeToSet = Opcode;
754 assert(opcodeType != (OpcodeType)-1 &&
755 "Opcode type not set");
756 assert(filter && "Filter not set");
758 if (Form == X86Local::AddRegFrm) {
759 if(Spec->modifierType != MODIFIER_MODRM) {
760 assert(opcodeToSet < 0xf9 &&
761 "Not enough room for all ADDREG_FRM operands");
763 uint8_t currentOpcode;
765 for (currentOpcode = opcodeToSet;
766 currentOpcode < opcodeToSet + 8;
768 tables.setTableFields(opcodeType,
774 Spec->modifierType = MODIFIER_OPCODE;
775 Spec->modifierBase = opcodeToSet;
777 // modifierBase was set where MODIFIER_MODRM was set
778 tables.setTableFields(opcodeType,
785 tables.setTableFields(opcodeType,
791 Spec->modifierType = MODIFIER_NONE;
792 Spec->modifierBase = opcodeToSet;
800 #define TYPE(str, type) if (s == str) return type;
801 OperandType RecognizableInstr::typeFromString(const std::string &s,
804 bool hasOpSizePrefix) {
806 // For SSE instructions, we ignore the OpSize prefix and force operand
808 TYPE("GR16", TYPE_R16)
809 TYPE("GR32", TYPE_R32)
810 TYPE("GR64", TYPE_R64)
813 // For instructions with a REX_W prefix, a declared 32-bit register encoding
815 TYPE("GR32", TYPE_R32)
817 if(!hasOpSizePrefix) {
818 // For instructions without an OpSize prefix, a declared 16-bit register or
819 // immediate encoding is special.
820 TYPE("GR16", TYPE_R16)
821 TYPE("i16imm", TYPE_IMM16)
823 TYPE("i16mem", TYPE_Mv)
824 TYPE("i16imm", TYPE_IMMv)
825 TYPE("i16i8imm", TYPE_IMMv)
826 TYPE("GR16", TYPE_Rv)
827 TYPE("i32mem", TYPE_Mv)
828 TYPE("i32imm", TYPE_IMMv)
829 TYPE("i32i8imm", TYPE_IMM32)
830 TYPE("GR32", TYPE_Rv)
831 TYPE("i64mem", TYPE_Mv)
832 TYPE("i64i32imm", TYPE_IMM64)
833 TYPE("i64i8imm", TYPE_IMM64)
834 TYPE("GR64", TYPE_R64)
835 TYPE("i8mem", TYPE_M8)
836 TYPE("i8imm", TYPE_IMM8)
838 TYPE("VR128", TYPE_XMM128)
839 TYPE("f128mem", TYPE_M128)
840 TYPE("FR64", TYPE_XMM64)
841 TYPE("f64mem", TYPE_M64FP)
842 TYPE("FR32", TYPE_XMM32)
843 TYPE("f32mem", TYPE_M32FP)
845 TYPE("i128mem", TYPE_M128)
846 TYPE("i64i32imm_pcrel", TYPE_REL64)
847 TYPE("i32imm_pcrel", TYPE_REL32)
848 TYPE("SSECC", TYPE_IMM8)
849 TYPE("brtarget", TYPE_RELv)
850 TYPE("brtarget8", TYPE_REL8)
851 TYPE("f80mem", TYPE_M80FP)
852 TYPE("lea32mem", TYPE_LEA)
853 TYPE("lea64_32mem", TYPE_LEA)
854 TYPE("lea64mem", TYPE_LEA)
855 TYPE("VR64", TYPE_MM64)
856 TYPE("i64imm", TYPE_IMMv)
857 TYPE("opaque32mem", TYPE_M1616)
858 TYPE("opaque48mem", TYPE_M1632)
859 TYPE("opaque80mem", TYPE_M1664)
860 TYPE("opaque512mem", TYPE_M512)
861 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
862 TYPE("DEBUG_REG", TYPE_DEBUGREG)
863 TYPE("CONTROL_REG_32", TYPE_CR32)
864 TYPE("CONTROL_REG_64", TYPE_CR64)
865 TYPE("offset8", TYPE_MOFFS8)
866 TYPE("offset16", TYPE_MOFFS16)
867 TYPE("offset32", TYPE_MOFFS32)
868 TYPE("offset64", TYPE_MOFFS64)
869 errs() << "Unhandled type string " << s << "\n";
870 llvm_unreachable("Unhandled type string");
874 #define ENCODING(str, encoding) if (s == str) return encoding;
875 OperandEncoding RecognizableInstr::immediateEncodingFromString
876 (const std::string &s,
877 bool hasOpSizePrefix) {
878 if(!hasOpSizePrefix) {
879 // For instructions without an OpSize prefix, a declared 16-bit register or
880 // immediate encoding is special.
881 ENCODING("i16imm", ENCODING_IW)
883 ENCODING("i32i8imm", ENCODING_IB)
884 ENCODING("SSECC", ENCODING_IB)
885 ENCODING("i16imm", ENCODING_Iv)
886 ENCODING("i16i8imm", ENCODING_IB)
887 ENCODING("i32imm", ENCODING_Iv)
888 ENCODING("i64i32imm", ENCODING_ID)
889 ENCODING("i64i8imm", ENCODING_IB)
890 ENCODING("i8imm", ENCODING_IB)
891 errs() << "Unhandled immediate encoding " << s << "\n";
892 llvm_unreachable("Unhandled immediate encoding");
895 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
896 (const std::string &s,
897 bool hasOpSizePrefix) {
898 ENCODING("GR16", ENCODING_RM)
899 ENCODING("GR32", ENCODING_RM)
900 ENCODING("GR64", ENCODING_RM)
901 ENCODING("GR8", ENCODING_RM)
902 ENCODING("VR128", ENCODING_RM)
903 ENCODING("FR64", ENCODING_RM)
904 ENCODING("FR32", ENCODING_RM)
905 ENCODING("VR64", ENCODING_RM)
906 errs() << "Unhandled R/M register encoding " << s << "\n";
907 llvm_unreachable("Unhandled R/M register encoding");
910 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
911 (const std::string &s,
912 bool hasOpSizePrefix) {
913 ENCODING("GR16", ENCODING_REG)
914 ENCODING("GR32", ENCODING_REG)
915 ENCODING("GR64", ENCODING_REG)
916 ENCODING("GR8", ENCODING_REG)
917 ENCODING("VR128", ENCODING_REG)
918 ENCODING("FR64", ENCODING_REG)
919 ENCODING("FR32", ENCODING_REG)
920 ENCODING("VR64", ENCODING_REG)
921 ENCODING("SEGMENT_REG", ENCODING_REG)
922 ENCODING("DEBUG_REG", ENCODING_REG)
923 ENCODING("CONTROL_REG_32", ENCODING_REG)
924 ENCODING("CONTROL_REG_64", ENCODING_REG)
925 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
926 llvm_unreachable("Unhandled reg/opcode register encoding");
929 OperandEncoding RecognizableInstr::memoryEncodingFromString
930 (const std::string &s,
931 bool hasOpSizePrefix) {
932 ENCODING("i16mem", ENCODING_RM)
933 ENCODING("i32mem", ENCODING_RM)
934 ENCODING("i64mem", ENCODING_RM)
935 ENCODING("i8mem", ENCODING_RM)
936 ENCODING("f128mem", ENCODING_RM)
937 ENCODING("f64mem", ENCODING_RM)
938 ENCODING("f32mem", ENCODING_RM)
939 ENCODING("i128mem", ENCODING_RM)
940 ENCODING("f80mem", ENCODING_RM)
941 ENCODING("lea32mem", ENCODING_RM)
942 ENCODING("lea64_32mem", ENCODING_RM)
943 ENCODING("lea64mem", ENCODING_RM)
944 ENCODING("opaque32mem", ENCODING_RM)
945 ENCODING("opaque48mem", ENCODING_RM)
946 ENCODING("opaque80mem", ENCODING_RM)
947 ENCODING("opaque512mem", ENCODING_RM)
948 errs() << "Unhandled memory encoding " << s << "\n";
949 llvm_unreachable("Unhandled memory encoding");
952 OperandEncoding RecognizableInstr::relocationEncodingFromString
953 (const std::string &s,
954 bool hasOpSizePrefix) {
955 if(!hasOpSizePrefix) {
956 // For instructions without an OpSize prefix, a declared 16-bit register or
957 // immediate encoding is special.
958 ENCODING("i16imm", ENCODING_IW)
960 ENCODING("i16imm", ENCODING_Iv)
961 ENCODING("i16i8imm", ENCODING_IB)
962 ENCODING("i32imm", ENCODING_Iv)
963 ENCODING("i32i8imm", ENCODING_IB)
964 ENCODING("i64i32imm", ENCODING_ID)
965 ENCODING("i64i8imm", ENCODING_IB)
966 ENCODING("i8imm", ENCODING_IB)
967 ENCODING("i64i32imm_pcrel", ENCODING_ID)
968 ENCODING("i32imm_pcrel", ENCODING_ID)
969 ENCODING("brtarget", ENCODING_Iv)
970 ENCODING("brtarget8", ENCODING_IB)
971 ENCODING("i64imm", ENCODING_IO)
972 ENCODING("offset8", ENCODING_Ia)
973 ENCODING("offset16", ENCODING_Ia)
974 ENCODING("offset32", ENCODING_Ia)
975 ENCODING("offset64", ENCODING_Ia)
976 errs() << "Unhandled relocation encoding " << s << "\n";
977 llvm_unreachable("Unhandled relocation encoding");
980 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
981 (const std::string &s,
982 bool hasOpSizePrefix) {
983 ENCODING("RST", ENCODING_I)
984 ENCODING("GR32", ENCODING_Rv)
985 ENCODING("GR64", ENCODING_RO)
986 ENCODING("GR16", ENCODING_Rv)
987 ENCODING("GR8", ENCODING_RB)
988 errs() << "Unhandled opcode modifier encoding " << s << "\n";
989 llvm_unreachable("Unhandled opcode modifier encoding");